MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 857

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 15-119
15.5.4.3.9
Annex 36A in IEEE 802.3z describes several jitter test patterns. These can be configured to be sent by
writing the jitter diagnostics register. See the register description for more information. In may be wise to
auto-negotiate and advertise a remote fault signaling of offline prior to beginning the test patterns.
Figure 15-115
Freescale Semiconductor
4–15
Bits
0
1
2
3
Offset 0x10
Reset
W
R
1000X Half
1000T Half
1000X Full
1000T Full
Enable
describes the fields of the EXST register.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Jitter
describes the definition for the JD register.
Name
Jitter Diagnostics Register (JD)
0
—
1
Jitter Select
1000X full-duplex capability. Returns 1 on read. This bit is read-only.
0 PHY cannot operation in 1000BASE-X full-duplex mode.
1 PHY can operate in 1000BASE-X full-duplex mode.
1000X half-duplex capability. Returns 0 on read. This bit is read-only.
0 PHY cannot operation in 1000BASE-X half-duplex mode.
1 PHY can operate in 1000BASE-X half-duplex mode.
1000T full-duplex capability. Returns 1 on read. This bit is read-only.
0 PHY cannot operation in 1000BASE-T full-duplex mode.
1 PHY can operate in 1000BASE-T full-duplex mode.
1000T half-duplex capability. Returns 0 on read. This bit is read-only.
0 PHY cannot operation in 1000BASE-T half-duplex mode.
1 PHY can operate in 1000BASE-T half-duplex mode.
Reserved
Figure 15-115. Jitter Diagnostics Register Definition
Table 15-119. EXST Field Descriptions
3
4
—
5
6
All zeros
Description
Custom Jitter Pattern
Enhanced Three-Speed Ethernet Controllers
Access: Read/Write
15-125
15