MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 775

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.5.3.2.3
This register defines the default value for the VLAN Ethertype and control word when VLAN tags are
automatically inserted by the eTSEC, and no per-frame VLAN data is supplied by software. On receive,
this register defines a customizable VLAN Ethertype for automatic deletion. Note that an Ethertype of
0x8808 (Control Word) is not permitted as a custom VLAN tag. Frames with an Ethertype of 0x8808 will
be dropped by the receiver. In the case of frames containing stacked VLAN tags, this register defines the
tag associated with the outer or metropolitan area VLAN.
Table 15-17
Freescale Semiconductor
16–18
20–31
24–31
0–15
Bits
Bits
19
23
Offset eTSEC1:0x2_4108; eTSEC3:0x2_5108
Reset 1
W
R
Name
Name
TAG
TXF7 Transmit frame event occurred on ring 7. Set by the eTSEC if IEVENT[TXF] was set in relation to transmitting
PRI
CFI
VID
0
—
0
describes the fields of the DFVLAN register.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
This is the default Ethertype used to tag VLAN frames. On transmit, this tag is inserted ahead of the VLAN
control word; TAG should be set to 0x8100 for IEEE 802.1Q VLAN. On receive, an Ethertype matching TAG or
an Ethertype of 0x8100 marks a VLAN-tagged frame.
Note that if using DFVLAN to set a custom ethertype (that is, using a value other than 0x8100), packets
received with a custom tag are not counted by any of the RMON counters. Affected counters include TRMGV,
RMCA, RBCA, RXCF, RXPF, RXUO, RALN, RFLR, ROVR, RJBR, TMCA, TBCA, TXPF, TXCF.
This is the default value used for the IEEE Std. 802.1Q canonical format indicator.
This is the default value used for the virtual-LAN identifier in VLAN-tagged frames. A value of zero is defined
as the null VLAN, however field PRI may be still set independently.
This is the default value used for the IEEE Std. 802.1p frame priority.
Default VLAN Control Word Register (DFVLAN)
0
a frame from this ring.
Reserved
0
0
0
0
Table 15-16. TSTAT Field Descriptions (continued)
1
TAG
Figure 15-13. DFVLAN Register Definition
Table 15-17. DFVLAN Field Descriptions
0
0
0
0
0
0
0
15 16
0
Description
Description
0
Figure 15-13
PRI
0
18
0
CFI
19
0
20
Enhanced Three-Speed Ethernet Controllers
0
describes the DFVLAN register.
0
0
0
0
0
VID
0
Access: Read/Write
0
0
0
15-43
0
31
0