MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 858

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Table 15-120
15.5.4.3.10 TBI Control Register (TBICON)
Figure 15-116
Offset 0x11
15-126
Reset
6–15
Bits
1–3
4–5
0
W
R
Soft_Reset
Custom Jitter
Jitter Enable Jitter enable. This bit is cleared by default.
Jitter Select
0
0
Pattern
Name
—
describes the fields of the JD register.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
describes the definition for the TBICON register.
—
0
1
0 Normal transmit operation.
1 Enable the TBI to transmit the jitter test patterns defined in IEEE 802.3z 36A.
Selects the jitter pattern to be transmitted in diagnostics mode. Encoding of this field is shown in the
following table. Default is 00.
Reserved
Used in conjunction with jitter (pattern) select and jitter (diagnostic) enable; set this field to the desired
custom pattern which is continuously transmitted. Its default is 0x000.
User defined uses custom jitter pattern, bits 6–15
High frequency (+/- D21.5)
1010101010101010101010101010101010101010…
Mixed frequency (+/- K28.5)
1111101011000001010011111010110000010100…
Low frequency
1111100000111110000011111000001111100000…
Complex pattern (10’h17c,10’h0c9,10’h0e5,10’h2a3, 10’h17c,...)
Square Wave (- K28.7)
0011111000001111100000111110000011111000…
Reserved
Reserved
Disable
Rx Dis
0
2
Disable
Tx Dis
Figure 15-116. TBI Control Register Definition
0
3
Table 15-120. JD Field Descriptions
0
4
Jitter Pattern Select
—
0
0
6
Sense
AN
7
0
Description
0
8
—
0
9
Select
Clock
10
0
bit[1]
Mode
0
0
0
0
1
1
1
1
MII
11
1
Freescale Semiconductor
bit[2]
0
0
1
1
0
0
1
1
12
0
bit[3]
13
0
0
1
0
1
0
1
0
1
Access: Mixed
—
14
0
15
0