MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 439

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.3.7.3
The internal interrupt vector/priority registers (IIVPRs), shown in
format as the GTVPRs, except that they apply to the internal interrupt sources listed in
interrupts are all level-sensitive.
Table 10-42
Freescale Semiconductor
2–30
Offset IIVPR0–7 0x5_0200, 0x5_0220, 0x5_0240, 0x5_0260, 0x5_0280, 0x5_02A0, 0x5_02C0, 0x5_02E0
Bits Name
Reset
Bits
31
2–7
0
1
W
R
IIVPR8–15 0x5_0300, 0x5_0320, 0x5_0340, 0x5_0360, 0x5_0380, 0x5_03A0, 0x5_03C0, 0x5_03E0
IIVPR16–23 0x5_0400, 0x5_0420, 0x5_0440, 0x5_0460, 0x5_0480, 0x5_04A0, 0x5_04C0, 0x5_04E0
IIVPR24–31 0x5_0500, 0x5_0520, 0x5_0540, 0x5_0560, 0x5_0580, 0x5_05A0, 0x5_05C0, 0x5_05E0
IIVPR32–39 0x5_0600, 0x5_0620, 0x5_0640, 0x5_0660, 0x5_0680, 0x5_06A0, 0x5_06C0, 0x5_06E0
IIVPR40–47 0x5_0700, 0x5_0720, 0x5_0740, 0x5_0760, 0x5_0780, 0x5_07A0, 0x5_07C0, 0x5_07E0
MSK
P0
—
1
0
Name
MSK
—
A
Reserved
Processor 0. Indicates that processor 0 handles any interrupt. P0 is meaningful only in a multi-core device. In a
single-core device, all interrupts that are serviced internally are directed to processor 0. Permanently set and read
only.
1 Interrupt directed to processor 0.
A
0
1
describes the IIVPR fields.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Internal Interrupt Vector/Priority Registers (IIVPR0–IIVPR47)
Because all internal interrupts are active-high, clearing any IIVPRn polarity
field disables that interrupt. Care should be taken to ensure this field is not
inadvertently corrupted when loading or reloading IIVPRs with priority,
mask, or vector data.
0
2
Mask. Mask interrupts from this source.
0 An interrupt request is generated when the corresponding IPR field is set.
1 Further interrupts from this source are disabled.
Activity. Indicates an interrupt has been requested or is in-service. Note this field is read only. The VECTOR
and PRIORITY values should not be changed while IIVPR n [A] is set.
0 No current interrupt activity associated with this source.
1 The interrupt field for this source is set in the IPR or ISR.
Reserved
0
Figure 10-38. Internal Interrupt Vector/Priority Registers (IIVPRs)
0
—
0
Table 10-41. EIDR n Field Descriptions (continued)
0
0
7
Table 10-42. IIVPR n Field Descriptions
P
1
8
9
0
—
0
11 12
0
0
PRIORITY
NOTE
0
Description
0
Description
15 16
0
0
0
Figure
0
0 0 0 0 0 0 0 0 0 0 0 0
10-38, have the same fields and
Programmable Interrupt Controller
VECTOR
Table
10-42. These
Access: Mixed
10-41
31
0