MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 221

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.2
Embedded 32-bit processors implement the following types of software-accessible registers:
In this chapter, SPRs are grouped by function as follows:
Freescale Semiconductor
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Architecture-defined registers that are accessed as part of instruction execution. These include the
following:
— Registers used for computation. These include the following:
— Condition register (CR)—Used to record conditions such as overflows and carries that occur
— Machine state register (MSR)—Used by the operating system to configure parameters such as
Special-purpose registers (SPRs) are accessed explicitly using mtspr and mfspr instructions.
These registers are listed in
Freescale EIS– and e500-defined SPRs that are accessed explicitly using mtspr and mfspr are
listed in
Freescale EIS–defined performance monitor registers (PMRs). These registers are similar to SPRs,
but are accessed with Freescale EIS–defined move to and move from PMR instructions (mtpmr
and mfpmr).
Section 6.4, “Registers for Branch Operations,”
register (LR).
Section 6.5, “Processor Control Registers”
Section 6.6, “Timer Registers”
Section 6.7, “Interrupt Registers”
Section 6.8, “Software-Use SPRs (SPRG0–SPRG7 and USPRG0),”
software use.
Section 6.9, “Branch Target Buffer (BTB) Registers,”
support the e500 tabs.
Section 6.10, “Hardware Implementation-Dependent Registers,”
Section 6.11, “L1 Cache Configuration Registers”
Register Model for 32-Bit Implementations
– General-purpose registers (GPRs)—The 32 GPRs hold source and destination operands for
– Integer exception register (XER)—Bits in this register are set based on the operation of an
These registers are described in
as a result of executing arithmetic instructions (including those implemented by the SPE). The
CR is described in
user/supervisor mode, address space, and enabling of asynchronous interrupts. This register is
described in
SPRs.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
load, store, arithmetic, and computational instructions, and to read and write to other
registers. The e500 implements these as 64-bit registers for use with 64-bit load, store, and
merge instructions, as described in
instruction considered as a whole, not on intermediate results. (For example, the Subtract
from Carrying instruction (subfc), the result of which is specified as the sum of three values,
sets bits in the XER based on the entire operation, not on an intermediate sum.)
Table 6-2
Section 6.5.1, “Machine State Register (MSR),”
in
Section 6.2.1, “Special-Purpose Registers (SPRs).”
Section 6.4, “Registers for Branch Operations.”
Table 6-1
Section 6.3, “Registers for Computational Operations.”
in
Section 6.2.1, “Special-Purpose Registers (SPRs).”
Section 6.3.1, “General-Purpose Registers (GPRs).”
describes the count register (CTR) and the link
describes e500-specific registers defined to
grouped with processor control
describes HID0 and HID1.
describes SPRs defined for
Core Register Summary
6-3