MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1117

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.3.8.3.13 PCI Express Prefetchable Base Upper 32 Bits Register—0x28
The PCI Express prefetchable memory base upper 32 bits register is shown in
Table 18-66
18.3.8.3.14 PCI Express Prefetchable Limit Upper 32 Bits Register—0x2C
The PCI Express prefetchable memory base upper 32 bits register is shown in
Table 18-67
18.3.8.3.15 PCI Express I/O Base Upper 16 Bits Register—0x30
Note that this device does not support inbound I/O transactions. The I/O base upper 16 bits register is
shown in
Freescale Semiconductor
31–0
Offset 0x28
Bits
Offset 0x2C
Reset
Reset
31–0
Offset 0x30
Reset
Bits
W
W
W
R
R
R
31
31
PF Base Upper 32 Bits Specifies bits 64:32 of the prefetchable memory space start address when the address
Figure
PF Limit Upper 32 Bits Specifies bits 64–32 of the prefetchable memory space ending address when the address
15
describes the PCI Express prefetchable memory base upper 32 bits register fields.
describes the PCI Express prefetchable memory limit upper 32 bits register fields.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Name
Name
18-72.
Figure 18-70. PCI Express Prefetchable Base Upper 32 Bits Register
Figure 18-71. PCI Express Prefetchable Limit Upper 32 Bits Register
Table 18-66. PCI Express Prefetchable Base Upper 32 Bits Register
Table 18-67. PCI Express Prefetchable Limit Upper 32 Bits Register
Figure 18-72. PCI Express I/O Base Upper 16 Bits Register
decode type field in the prefetchable memory base register is 0x01.
decode type field in the prefetchable memory limit register is 0x01.
PF Base Upper 32 Bits
I/O Base Upper 16 Bits
PF Limit Upper 32 Bits
All zeros
All zeros
All zeros
Description
Description
Figure
Figure
PCI Express Interface Controller
18-70.
18-71.
Access: Read/Write
Access: Read/Write
Access: Read-only
18-63
0