MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 24

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Paragraph
Number
14.2
14.3
14.3.1
14.3.1.1
14.3.1.2
14.3.1.2.1
14.3.1.2.2
14.3.1.2.3
14.3.1.2.4
14.3.1.3
14.3.1.4
14.3.1.5
14.3.1.6
14.3.1.7
14.3.1.8
14.3.1.9
14.3.1.10
14.3.1.11
14.3.1.12
14.3.1.13
14.3.1.14
14.3.1.15
14.3.1.16
14.4
14.4.1
14.4.1.1
14.4.1.2
14.4.1.3
14.4.1.4
14.4.1.5
14.4.1.6
14.4.1.7
14.4.2
14.4.2.1
14.4.2.2
14.4.2.2.1
14.4.2.2.2
14.4.2.2.3
14.4.2.2.4
14.4.2.2.5
14.4.2.3
xxiv
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
External Signal Descriptions ......................................................................................... 14-4
Memory Map/Register Definition ................................................................................. 14-8
Functional Description................................................................................................. 14-32
Register Descriptions............................................................................................... 14-10
Basic Architecture.................................................................................................... 14-33
General-Purpose Chip-Select Machine (GPCM)..................................................... 14-36
Base Registers (BR0–BR7) ................................................................................. 14-10
Option Registers (OR0–OR7).............................................................................. 14-12
UPM Memory Address Register (MAR)............................................................. 14-17
UPM Mode Registers (MxMR) ........................................................................... 14-17
Memory Refresh Timer Prescaler Register (MRTPR) ........................................ 14-20
UPM Data Register (MDR) ................................................................................. 14-20
SDRAM Machine Mode Register (LSDMR) ...................................................... 14-21
UPM Refresh Timer (LURT)............................................................................... 14-23
SDRAM Refresh Timer (LSRT).......................................................................... 14-23
Transfer Error Status Register (LTESR) .............................................................. 14-24
Transfer Error Check Disable Register (LTEDR)................................................ 14-25
Transfer Error Interrupt Enable Register (LTEIR) .............................................. 14-26
Transfer Error Attributes Register (LTEATR) ..................................................... 14-27
Transfer Error Address Register (LTEAR).......................................................... 14-29
Local Bus Configuration Register (LBCR) ......................................................... 14-29
Clock Ratio Register (LCRR).............................................................................. 14-30
Address and Address Space Checking ................................................................ 14-33
External Address Latch Enable Signal (LALE) .................................................. 14-33
Data Transfer Acknowledge (TA) ....................................................................... 14-34
Data Buffer Control (LBCTL)............................................................................. 14-35
Atomic Operation ................................................................................................ 14-35
Parity Generation and Checking (LDP)............................................................... 14-36
Bus Monitor ......................................................................................................... 14-36
Timing Configuration .......................................................................................... 14-37
Chip-Select Assertion Timing ............................................................................. 14-39
External Access Termination (LGTA) ................................................................. 14-46
Address Mask .................................................................................................. 14-12
Option Registers (ORn)—GPCM Mode ......................................................... 14-13
Option Registers (ORn)—UPM Mode ............................................................ 14-15
Option Registers (ORn)—SDRAM Mode ...................................................... 14-16
Programmable Wait State Configuration......................................................... 14-40
Chip-Select and Write Enable Negation Timing ............................................. 14-40
Relaxed Timing ............................................................................................... 14-41
Output Enable (LOE) Timing .......................................................................... 14-43
Extended Hold Time on Read Accesses .......................................................... 14-43
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Freescale Semiconductor
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