MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 756

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
15.5.3.1.2
The controller ID register (TSEC_ID2) is a read-only register. The TSEC_ID2 register is used to identify
the eTSEC block configuration.
Table 15-6
15.5.3.1.3
Interrupt events cause bits in the IEVENT register to be set. Software may poll this register at any time to
check for pending interrupts. If an event occurs and its corresponding enable bit is set in the interrupt mask
register (IMASK), the event also causes a hardware interrupt at the PIC. A bit in the interrupt event register
is cleared by writing a 1 to that bit position. A write of 0 has no effect.
15-24
10–15
16–23
24–31
Bits
0–9
Offset eTSEC1:0x2_4004; eTSEC3:0x2_5004
Reset 0
W
R
TSEC_CFG
0
TSEC_INT
describes the fields of the TSEC_ID2 register.
Name
0
—
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Controller ID Register (TSEC_ID2)
Interrupt Event Register (IEVENT)
0
0
0
Reserved
Interface mode support.
Reserved
Value identifies configuration options of the eTSEC.
00 eTSEC multiple ring, Rx TOE, Filer and Tx TOE supports are off
F0 eTSEC multiple ring, Rx TOE, Filer and Tx TOE supports are on
30 eTSEC multiple ring support is OFF and Rx TOE, Filer and Tx TOE supports are on
50 eTSEC multiple ring and filer supports are OFF and Rx TOE and Tx TOE supports are on
—
0
0
0
Table 15-6. TSEC_ID2 Field Descriptions
0
Bit
10
11
12
13
14
15
0
9
Figure 15-3. TSEC_ID2 Register
10
1
0 Ethernet mode not supported
1 Ethernet mode supported
0 FIFO mode not supported
1 FIFO mode supported
Reserved
0 Can be configured to run in FIFO 8-bit mode
1 FIFO 8-bit mode off
0 Can be configured to run in Ethernet normal/full mode
1 Ethernet normal/full mode off
0 Can be configured to run in Ethernet reduced mode
1 Ethernet reduced mode off
TSEC_INT
0
0
0
15 16
0
0
Description
0
0
Mode
0
—
0
0
0
23 24
0
1
Freescale Semiconductor
1
1
TSEC_CFG
Access: Read only
1
0
0
0
31
0