MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 430

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programmable Interrupt Controller
10.3.3.7
Figure 10-24
Table 10-28
10.3.4
The twelve performance monitor mask registers consist of four sets of three 32-bit registers—PMnMR0,
PMnMR1, and PMnMR2. Each set can be configured to select one interrupt source (IPI, timer, message,
or external) to generate a performance monitor event. The performance monitor can be configured to track
this event in the performance monitor local control registers. See
Local Control Registers (PMLCAn, PMLCBn).”
10.3.4.1
Figure 10-25
PMnMR2 register. Because each unreserved bit in the 96-bit set (PMnMR0/1/2) specifies a different
interrupt, only one bit in each set can be unmasked at a time. Unmasking more than one bit per set is
considered a programming error and results in unpredictable behavior.
10-32
16–31
0–15
Offset 0x4_1344
Offset PM0MR0: 0x4_1350, PM1MR0: 0x4_1370, PM2MR0: 0x4_1390’ PM3MR0: 0x4_13B0
Reset
Bits
Reset 0
W
W
R
R
0
0
Name
INT n
—
0
shows CISR2 fields.
Performance Monitor Mask Registers (PMMRs)
describes the CISR2 register.
shows the PMnMR0 registers. Each PMnMR0 register is associated with a PMnMR1 and a
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
Critical Interrupt Summary Register 2 (CISR2)
Performance Monitor n Mask Registers 0 (PM n MR0)
Internal interrupts 32–47. Bit 0 represents INT32. Bit 15 represents INT47.
0 Corresponding interrupt is not active or not directed to cint .
1 The corresponding interrupt is active and is directed to the cint (if the corresponding xIDR[CI] is set).
Reserved
0
—
Figure 10-25. Performance Monitor n Mask Registers 0 (PM n MR0)
0
Figure 10-24. Critical Interrupt Summary Register 2 (CISR2)
0
0
INT n
0
7
8
1
Table 10-28. CISR2 Field Descriptions
1
IPI
1
11 12
1
1
TIMER
1
1
All zeros
15 16
15 16
1
Description
1
MSG
1
1
Section 20.3.2.2, “Performance Monitor
19 20
1
1
1
1
1
—
1
Freescale Semiconductor
1
EXT
1
Access: Read/Write
Access: Read only
1
1
1
1
31
31
1