MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 356

MPU POWERQUICC III 783-PBGA

MPC8544VTALF

Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8544VTALF

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
DDR Memory Controller
9.4.1.17
The DDR IP block revision 1 register, shown in
ID, along with major and minor revision information.
Table 9-23
9.4.1.18
The DDR IP block revision 2 register, shown in
integration and configuration options.
Table 9-24
9-32
1
Offset 0xBF8
Reset n
16–23
24–31
16–23
24–31
0–15
8–15
Bits
Bits
0–7
For reset values, see
Offset 0xBFC
Reset 0
W
R
W
R
0
1
IP_MN Minor revision. This is currently set to 0x00.
IP_MJ Major revision. This is currently set to 0x02.
IP_CFG IP block configuration options
Name
IP_ID
IP_INT
Name
0
n
describes the DDR_IP_REV1 fields.
describes the DDR_IP_REV2 fields.
0
DDR IP Block Revision 1 (DDR_IP_REV1)
n
DDR IP Block Revision 2 (DDR_IP_REV2)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
IP block ID. For the DDR controller, this value is 0x0002.
n
0
Reserved
IP block integration options
Reserved
n
0 0
Table 9-23
n
n
Figure 9-18. DDR IP Block Revision 1 (DDR_IP_REV1)
Figure 9-19. DDR IP Block Revision 2 (DDR_IP_REV2)
0
IP_ID
n
.
Table 9-23. DDR_IP_REV1 Field Descriptions
Table 9-24. DDR_IP_REV2 Field Descriptions
0 0
n
7
n
n
8
n
n n n n n n n 0 0 0 0 0 0 0 0 n n n n n n n n
n
n
IP_INT
n
Figure
Figure
n
15 16
n
Description
9-18, provides read-only fields with the IP block
9-19, provides read-only fields with the IP block
Description
15 16
n
n
n
IP_MJ
n
n
n
n
23 24
n
23 24
n
Freescale Semiconductor
n
Access: Read Only
n
IP_CFG
Access: Read Only
IP_MN
n
n
n
n
31
31
n

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