MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1282

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Complete List of Configuration, Control, and Status Registers
B-16
0x2_4034–
0x2_4118–
0x2_4148–
0x2_41AC
0x2_401C
0x2_402C
0x2_404C
0x2_410C
0x2_413C
0x2_417C
0x2_418C
0x2_419C
0x2_4014
0x2_4018
0x2_4020
0x2_4024
0x2_4028
0x2_4030
0x2_4100
0x2_4104
0x2_4108
0x2_4110
0x2_4114
0x2_4140
0x2_4144
0x2_4180
0x2_4184
0x2_4188
0x2_4190
0x2_4194
0x2_4198
0x2_41A0
0x2_41A4
0x2_41A8
0x2_41B0
0x2_41B4
Offset
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
IMASK—Interrupt mask register
EDIS—Error disabled register
Reserved
ECNTRL—Ethernet control register
Reserved
PTV—Pause time value register
DMACTRL—DMA control register
TBIPA—TBI PHY address register
Reserved
TCTRL—Transmit control register
TSTAT—Transmit status register
DFVLAN*—Default VLAN control word
Reserved
TXIC—Transmit interrupt coalescing register
TQUEUE*—Transmit queue control register
Reserved
TR03WT*—TxBD Rings 0–3 round-robin weightings
TR47WT*—TxBD Rings 4–7 round-robin weightings
Reserved
TBDBPH*—Tx data buffer pointer high bits
TBPTR0—TxBD pointer for ring 0
Reserved
TBPTR1*—TxBD pointer for ring 1
Reserved
TBPTR2*—TxBD pointer for ring 2
Reserved
TBPTR3*—TxBD pointer for ring 3
Reserved
TBPTR4*—TxBD pointer for ring 4
Reserved
TBPTR5*—TxBD pointer for ring 5
Reserved
TBPTR6*—TxBD pointer for ring 6
eTSEC Transmit Control and Status Registers
Table B-1. Memory Map (continued)
Register
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x8100_0000
0x0000_0000
0x0000_0000
0x0000_8000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
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