MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 854

MPU POWERQUICC III 783-PBGA

MPC8544VTALF

Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8544VTALF

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8544VTALF
Manufacturer:
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Quantity:
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Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Enhanced Three-Speed Ethernet Controllers
15.5.4.3.5
Figure 15-111
Table 15-116
15-122
11–15
Bits
2–3
4–6
7–8
10
9
Offset 0x06
Reset
W
R
Remote
Duplex
Duplex
Pause
Name
Fault
Half
Full
0
describes the fields of the ANEX register.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
describes the definition for the ANEX register.
AN Expansion Register (ANEX)
The link partner’s remote fault condition is encoded in bits 2 and 3 of the base page. Values are shown in
the remote fault encoding field table below. This bit is read-only.
Reserved, should be cleared.
Encoding of the link partner’s PAUSE capability is shown in the PAUSE encoding table below. For priority
resolution information consult. This bit is read-only
Half-duplex capability. This bit is read-only.
0 Link partner is not capable of half-duplex mode.
1 Link partner is capable of half-duplex mode.
Full-duplex capability. This bit is read-only.
0 Link partner is not capable of full-duplex mode.
1 Link partner is capable of full-duplex mode.
Reserved, should be cleared.
PAUSE bit[8]
0
0
1
1
Table 15-115. ANLPBPA Field Descriptions (continued)
RF1 bit[3]
Figure 15-111. AN Expansion Register Definition
0
0
1
1
ASM_DIR bit[7]
0
1
0
1
RF2 bit[2]
0
1
0
1
No PAUSE
Asymmetric PAUSE toward link partner
Symmetric PAUSE
Both symmetric PAUSE and
Asymmetric PAUSE toward local device
No error, link OK
Offline
Link_Failure
Auto-Negotiation_Error
All zeros
Description
Description
Capability
12
NP Able
13
Freescale Semiconductor
Access: Read only
Page Rx’d
14
15

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