MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 915

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Other information about the link is also returned.(Extend Status, No pre, Remote Fault, An Ability, Link status, extend Ability)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
(Uses the PHY address (0) and Register address (1) placed in MIIMADD register),
Table 15-150. MII Mode Register Initialization Steps (continued)
read the MIIMSTAT register and check bit 10 (AN Done and Link is up)
RBASE0–RBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
TBASE0–TBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
Initialize (Empty) Receive Descriptor ring and fill with empty buffers
MACnADDR1/2[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize (Empty) Transmit Descriptor ring and fill buffers with Data
MIIMSTAT ---> [0000_0000_0000_0000_0000_0000_0010_0100]
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101]
DMACTRL[0000_0000_0000_0000_0000_0000_0000_0000]
GADDR n [0000_0000_0000_0000_0000_0000_0000_0000]
Check auto-negotiation attributes in the PHY as necessary.
IEVENT[0000_0000_0000_0000_0000_0000_0000_0000]
RCTRL[0000_0000_0000_0000_0000_0000_0000_0000]
IMASK[0000_0000_0000_0000_0000_0000_0000_0000]
Perform an MII Mgmt read cycle of Status Register.
Initialize MACnADDR1/2 (Optional)
Clear MIIMCOM[Read Cycle].
Initialize DMACTRL (Optional)
Initialize GADDR n (Optional)
Initialize RBASE0–RBASE7,
Set MIIMCOM[Read Cycle].
Initialize TBASE0–TBASE7,
Initialize RCTRL (Optional)
When MIIMIND[BUSY]=0,
Initialize IMASK (Optional)
Enable Transmit Queues
Enable Receive Queues
Clear IEVENT register,
Enable Rx and Tx,
Initialize RQUEUE
Initialize TQUEUE
Enhanced Three-Speed Ethernet Controllers
15-183