MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 278

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

L2 Look-Aside Cache/SRAM
The L2/SRAM can be accessed by the e500 core or the system interface through the ECM. The L2 cache
does not initiate transactions.
Figure 7-6
In SRAM mode, if a non–cache-line read or write transaction is not preceded by a cache-line write, an ECC
error occurs; such a non–cache-line write transaction cannot be allocated in the L2.
7.3
Table 7-3
In this table and in the register figures and field descriptions, the following access definitions apply:
7-8
.
•
•
•
•
•
Reserved fields are always ignored for the purposes of determining access type.
R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
Mixed indicates a combination of access types.
Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
shows the memory map for the L2/SRAM registers.
shows address connections of the e500 core and L2/SRAM.
Memory Map/Register Definition
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
e500 Coherency Module
e500 Coherency Module
SNOOP
RD1
e500 Core
Figure 7-5
(ECM)
Figure 7-6. Address Bus Connection of CCB
e500 Core
(ECM)
Figure 7-5. Data Bus Connection of CCB
RD2
MSTR
WR
shows the data bus connections of the e500 core and L2/SRAM.
128
128
64
RD IN
L2/SRAM
DOUT WR IN
ADDR_IN
L2/SRAM
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