MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 615

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.4
The communication channel provides a full-duplex asynchronous receiver and transmitter using an
operating frequency derived from the CCB clock signal.
The transmitter accepts parallel data with a write access to the transmitter holding register (UTHR). In
FIFO mode, the data is placed directly into an internal transmitter shift register, or into the transmitter
FIFO—see
by inserting the appropriate START, STOP, and optional parity bits. Finally, the registers output a
Freescale Semiconductor
DMS
DMS
DMS
DMS
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FEN
FEN
FEN
FEN
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Functional Description
Section 13.4.5, “FIFO Mode.”
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
DMA Mode
DMA Mode
DMA Mode
DMA Mode
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
TXRDY is set after the first character is loaded into the transmitter FIFO or UTHR.
TXRDY is set when the transmitter FIFO is full.
TXRDY is cleared when there are no characters in the transmitter FIFO or UTHR.
TXRDY is cleared when there are no characters in the transmitter FIFO or UTHR. TXRDY
remains clear when the transmitter FIFO is not yet full.
RXRDY is set when there are no characters in the receiver FIFO or URBR.
RXRDY is set when the trigger level has not been reached and there has been no time out.
RXRDY is cleared when there is at least one character in the receiver FIFO or URBR.
RXRDY is cleared when the trigger level or a time-out has been reached. RXRDY remains
cleared until the receiver FIFO is empty.
Table 13-22. UDSR[TXRDY] Cleared Conditions
Table 13-23. UDSR[RXRDY] Set Conditions
Table 13-21. UDSR[TXRDY] Set Conditions
Table 13-24. UDSR[RXRDY] Cleared
The transmitting registers convert the data to a serial bit stream,
Meaning
Meaning
Meaning
Meaning
DUART
13-19