MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 49

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure
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9-48
10-1
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Freescale Semiconductor
DDR Initialization Extended Address Configuration Register
DDR IP Block Revision 1 (DDR_IP_REV1) ....................................................................... 9-32
DDR IP Block Revision 2 (DDR_IP_REV2) ....................................................................... 9-32
Memory Data Path Error Injection Mask High Register (DATA_ERR_INJECT_HI) ......... 9-33
Memory Data Path Error Injection Mask Low Register (DATA_ERR_INJECT_LO)......... 9-33
Memory Data Path Error Injection Mask ECC Register (ERR_INJECT)............................ 9-34
Memory Data Path Read Capture High Register (CAPTURE_DATA_HI).......................... 9-34
Memory Data Path Read Capture Low Register (CAPTURE_DATA_LO) ......................... 9-35
Memory Data Path Read Capture ECC Register (CAPTURE_ECC)................................... 9-35
Memory Error Detect Register (ERR_DETECT) ................................................................. 9-36
Memory Error Disable Register (ERR_DISABLE).............................................................. 9-36
Memory Error Interrupt Enable Register (ERR_INT_EN)................................................... 9-37
Memory Error Attributes Capture Register (CAPTURE_ATTRIBUTES)........................... 9-38
Memory Error Address Capture Register (CAPTURE_ADDRESS) ................................... 9-39
Memory Error Extended Address Capture Register (CAPTURE_EXT_ADDRESS).......... 9-40
Single-Bit ECC Memory Error Management Register (ERR_SBE) .................................... 9-40
DDR Memory Controller Block Diagram ............................................................................ 9-42
Typical Dual Data Rate SDRAM Internal Organization....................................................... 9-43
Typical DDR SDRAM Interface Signals .............................................................................. 9-43
Example 256-Mbyte DDR SDRAM Configuration With ECC ............................................ 9-44
DDR SDRAM Burst Read Timing—ACTTORW = 3, MCAS Latency = 2 ........................ 9-56
DDR SDRAM Single-Beat (Double Word) Write Timing—ACTTOR ............................... 9-56
DDR SDRAM Single-Beat (Double Word) Write Timing—ACTTORW = 3...................... 9-56
DDR SDRAM 4-Beat Burst Write Timing—ACTTORW = 4 ............................................. 9-57
DDR SDRAM Clock Distribution Example for x8 DDR SDRAMs .................................... 9-58
DDR SDRAM Mode-Set Command Timing ........................................................................ 9-58
Registered DDR SDRAM DIMM Burst Write Timing ........................................................ 9-59
Write Timing Adjustments Example for Write Latency = 1 ................................................. 9-60
DDR SDRAM Bank Staggered Auto Refresh Timing.......................................................... 9-61
DDR SDRAM Power-Down Mode ...................................................................................... 9-62
DDR SDRAM Self-Refresh Entry Timing ........................................................................... 9-63
DDR SDRAM Self-Refresh Exit Timing ............................................................................. 9-63
Interrupt Sources Block Diagram ......................................................................................... 10-2
Pass-Through Mode Example ............................................................................................... 10-5
Block Revision Register 1 (BRR1) ..................................................................................... 10-18
Block Revision Register 2 (BRR2) ..................................................................................... 10-19
Feature Reporting Register (FRR) ...................................................................................... 10-19
Global Configuration Register (GCR) ................................................................................ 10-20
Vendor Identification Register (VIR).................................................................................. 10-21
Processor Initialization Register (PIR) ............................................................................... 10-21
(DDR_INIT_EXT_ADDR).............................................................................................. 9-31
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
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