MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 758

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
15-26
Bits
10
11
12
13
2
3
4
5
6
7
8
9
EBERR Internal bus error. This bit indicates that a system bus error occurred while a DMA transaction was
MSRO
Name
GTSC
BABT
BSY
TXC
TXE
TXB
TXF
LC
—
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0 No frame received and discarded.
1 Frame received and discarded.
underway. As a result, transferred data is expected to be partially or completely invalid.
0 No system bus error occurred.
1 System bus error occurred.
Reserved
size of its register.
0 MIB count not exceeding its register size.
1 MIB count exceeds its register size.
the transmitter is put into a pause state after completion of the frame currently being transmitted.
0 No graceful stop interrupt.
1 Graceful stop requested.
MAC’s maximum frame length register and MACCFG2[Huge Frame] is cleared. Frame truncation occurs
when this condition occurs.
0 Transmitted frame length not exceeding maximum frame length.
1 Transmitted frame length exceeding maximum frame length when MACCFG2[Huge Frame] = 0.
0 Control frame not transmitted.
1 Control frame transmitted.
TSTAT[THLT] to be set by the eTSEC. This bit is set whenever any transmit error occurs that causes the
transmitter to halt (EBERR, LC, CRL, XFUN).
0 No transmit channel error occurred.
1 Transmit channel error occurred.
set in its status word and was not the last buffer descriptor of the frame.
0 No transmit buffer descriptor updated.
1 Transmit buffer descriptor updated.
transmit buffer descriptor (TxBD) was updated. This only occurs if the I (interrupt) bit in the status word of
the buffer descriptor is set. The specific transmit queue that was updated has its TXF bit set in TSTAT.
0 No frame transmitted/TxBD not updated.
1 Frame transmitted/TxBD updated.
Reserved
Late collision. This bit indicates that a collision occurred beyond the collision window (slot time) in
half-duplex mode. The frame is truncated with a bad CRC and the remainder of the frame is discarded.
0 No late collision occurred.
1 Late collision occurred.
Busy condition interrupt. Indicates that a frame was received and discarded due to a lack of buffers.
MIB counter overflow. This interrupt is asserted if the count for one of the MIB counters has exceeded the
Graceful transmit stop complete. This interrupt is asserted for one of two reasons. Graceful stop means that
Babbling transmit error. This bit indicates that the transmitted frame length has exceeded the value in the
Transmit control interrupt. This bit indicates that a control frame was transmitted.
Transmit error. This bit indicates that an error occurred on the transmitted channel that has caused
Transmit buffer. This bit indicates that a transmit buffer descriptor was updated whose I (interrupt) bit was
Transmit frame interrupt. This bit indicates that a frame was transmitted and that the last corresponding
• A graceful stop, which was initiated by setting DMACTRL[GTS], is now complete.
• A transmission of a flow control PAUSE frame, which was initiated by setting TCTRL[TFC_PAUSE], is
now complete.
Table 15-7. IEVENT Field Descriptions (continued)
Description
Freescale Semiconductor