MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1086

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Offset 0xE08
Reset
Reset
PCI Express Interface Controller
18.3.6.2
The PCI Express error interrupt enable register, shown in
when the corresponding PCI Express error detect register bits are set.
Table 18-24
18-32
W
W
24–31
R
R
Bits
0–7
Bits
10
11
12
8
9
23
CRSTIE MISIE IOISIE CISIE CIEPIE IOIEPIE OACIE IOIAIE
16
0
CDNSCIE Completion with data not successful interrupt enable. When this bit is set and PEX_ERR_DR[CDNSC] = 1
PCACIE
PNMIE
PCTIE
Name
Name
IOIA
—
—
—
17
describes the fields of the PCI Express error interrupt enable register.
PCI Express Error Interrupt Enable Register (PEX_ERR_EN)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 18-23. PCI Express Error Detect Register Field Descriptions (continued)
Table 18-24. PCI Express Error Interrupt Enable Register Field Descriptions
Figure 18-25. PCI Express Error Interrupt Enable Register (PEX_ERR_EN)
I/O invalid address. An outbound I/O transaction with a translated address of greater than 4G was
detected.
1 A greater than 4G I/O address was detected
0 No greater than 4G I/O address detected
Reserved
Reserved
PCI Express completion time-out interrupt enable. When set and PEX_ERR_DR[PCT]=1 will generate an
interrupt.
1 Enable PCI Express completion time-out interrupt generation
0 Disable PCI Express completion time-out interrupt generation
Reserved
PCI Express CA completion interrupt enable. When set and PEX_ERR_DR[PCAC]=1 will generate an
interrupt.
1 Enable completion with CA status interrupt generation
0 Disable completion with CA status interrupt generation
PCI Express no map interrupt enable. When set and PEX_ERR_DR[PNM]=1 will generate an interrupt.
1 Enable no map PCI Express packet interrupt generation
0 Disable no map PCI Express packet interrupt generation
will generate an interrupt.
1 Enable completion with data non successful interrupt generation
0 Disable completion with data non successful interrupt generation
18
19
—
20
21
22
23
7
All zeros
All zeros
PCTIE
Description
Description
24
8
Figure
—
9
PCACIE PNMIE CDNSCIE CRSNCIE ICCAIE IACAIE
18-25, allows interrupts to be generated
10
11
—
12
Freescale Semiconductor
13
Access: Read/Write
14
15
31