MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 637

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.3.1.3
Figure 14-6
Table 14-9
14.3.1.4
The UPM machine mode registers (MAMR, MBMR and MCMR), shown in
configuration for the three UPMs.
Table 14-10
Freescale Semiconductor
0–31
Bits
Bits
Offset 0x070 (MAMR)
Reset
0
1
W
R
Offset 0x068
0x074 (MBMR)
0x078 (MCMR)
— RFEN OP UWPL
Reset
Name
0
Name
RFEN Refresh enable. Indicates that the UPM needs refresh services. This bit must be set for UPMA (refresh
—
A
W
describes the MAR fields.
R
shows the fields of the UPM memory address register (MAR).
describes UPM mode fields.
1
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
Address that can be output to the address signals under control of the AMX bits in the UPM RAM word.
Reserved
executor) if refresh services are required on any UPM assigned chip selects. If MAMR[RFEN] = 0, no refresh
services can be provided, even if UPMB and/or UPMC have their RFEN bit set.
0 Refresh services are not required
1 Refresh services are required
UPM Memory Address Register (MAR)
UPM Mode Registers (M x MR)
2
3
4
Figure 14-6. UPM Memory Address Register (MAR)
5
AM
Figure 14-7. UPM Mode Registers (M x MR)
Table 14-10. M x MR Field Descriptions
7
Table 14-9. MAR Field Descriptions
8
DS
9 10
G0CL
12
GPL4
13
All zeros
All zeros
Description
Description
14
A
RLF
17 18
WLF
21 22
Figure
TLF
Access: Read/Write
14-7, contain the
25 26
Access: Read/Write
Local Bus Controller
MAD
31
14-17
31