MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 267

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Reset
6.15.1
Freescale Semiconductor
35–50
51–52
53–54
Bits
32
33
34
W
R
PMGC0 (PMR400)
UPMGC0 (PMR384)
1
FAC PMIE FCECE
32
e500v2 only
FCECE Freeze counters on enabled condition or event
TBSEL Time base selector. Selects the time base bit that can cause a time base transition event (the event occurs
Name
PMIE
FAC
—
—
33
Global Control Register 0 (PMGC0, UPMGC0)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Freeze all counters. When FAC is set by hardware or software, PMLCx[FC] maintains its current value until
it is changed by software.
0 The PMCs are incremented (if permitted by other PM control bits).
1 The PMCs are not incremented.
0 Performance monitor interrupts are disabled.
1 Performance monitor interrupts are enabled and occur when an enabled condition or event occurs.
0 The PMCs can be incremented (if permitted by other PM control bits).
1 The PMCs can be incremented (if permitted by other PM control bits) only until an enabled condition or
Reserved, should be cleared.
when the selected bit changes from 0 to 1).
00 TB[63] (TBL[31])
01 TB[55] (TBL[23])
10 TB[51] (TBL[19])
11 TB[47] (TBL[15])
Time base transition events can be used to periodically collect information about processor activity. In
multiprocessor systems in which TB registers are synchronized among processors, time base transition
events can be used to correlate the performance monitor data obtained by the several processors. For this
use, software must specify the same TBSEL value for all processors in the system. Because the time-base
frequency is implementation-dependent, software should invoke a system service program to obtain the
frequency before choosing a value for TBSEL.
Reserved, should be cleared.
Performance monitor interrupt enable
Figure 6-58. Performance Monitor Global Control Register 0 (PMGC0),
event occurs. When an enabled condition or event occurs, PMGC0[FAC] is set. It is up to software to
clear FAC.
34
User Performance Monitor Global Control Register 0 (UPMGC0)
35
Table 6-43. PMGC0 Field Descriptions
—
All zeros
Description
50
TBSEL
51
52
1
Access: PMGC0: Supervisor- read/write
53 54
—
UPMGC0: Supervisor/user read only
TBEE
55
1
56
Core Register Summary
—
6-49
63