MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1084

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PCI Express Interface Controller
normally; however, write operations can clear but not set bits. A bit is cleared whenever the register is
written, and the data in the corresponding bit location is a 1. For example, to clear bit 6 and not affect any
other bits in the register, the value 0b0200_0000 is written to the register. When an error is detected the
appropriate error bit is set. Subsequent errors will set the appropriate error bits in the error detection
registers, but only the first error for a particular unit will have any relevant information captured. The
interrupt enable bits are used to allow or block the error reporting to the interrupt mechanism while the
disable bits are used to prevent or allow the setting of the status bits.
Table 18-23
18-30
Offset 0xE00
Reset
Reset
Bits
1–7
10
11
0
8
9
W w1c
W w1c
R
R CRST MIS
ME
16
0
Name
PCAC
PNM
PCT
ME
—
—
describes the fields of the PCI Express error detect register.
w1c
17
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
1
Multiple errors. Detecting multiple errors of the same type. An error is considered as multiple error when its
detect bit is set and the same error is occurring again. Note that this bit does not track the ordering of when
the error occurs.
1 Multiple errors were detected.
0 Multiple errors were not detected.
Reserved
PCI Express completion time-out. A completion time-out condition was detected for a non-posted,
outbound PCI Express transaction. An error response is sent back to the requestor.
1 A completion time-out on the PCI Express link was detected.
0 No completion time-out on the PCI Express link detected.
Reserved
PCI Express completer abort (CA) completion. A completion with CA status was received.
1 A completion with CA status was detected.
0 No completion with CA status detected.
PCI Express no map. Detect an inbound transaction that was not mapped to any inbound windows. In RC
mode, a completion without data (Cpl) packet with a UR completion status is sent back to the requester and
this bit is set. For EP mode, a Cpl packet with a UR completion status is sent back to the requester but will
not set this bit.
1 A no-map transaction was detected in RC mode.
0 No no-map transaction detected.
IOIS
w1c
18
Table 18-23. PCI Express Error Detect Register Field Descriptions
Figure 18-24. PCI Express Error Detect Register (PEX_ERR_DR)
w1c
CIS
19
CIEP IOIEP OAC
w1c
—
20
w1c
21
w1c
22
IOIA
w1c
23
7
All zeros
All zeros
PCT
Description
w1c
24
8
—
9
PCAC PNM CDNSC CRSNC ICCA IACA
w1c
10
w1c
11
—
w1c
12
Freescale Semiconductor
w1c
13
Access: w1c
w1c
14
w1c
15
31