MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 401

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.1.2
10.1.3
The int signal, which causes the external interrupt exception, is the main interrupt output from the PIC unit
to the processor core. Interrupts can alternately be configured as critical interrupts (in the destination
registers); these are reported to the core through the cint signal. The architecture implemented by the e500
core defines a separate critical interrupt type with its own save and restore registers (CSRR0 and CSRR1)
and return instruction (Return from Critical Interrupt, rfci). In addition to the external and critical
interrupts that are generated by the PIC, other conditions (shown in
(and wake up the core when it is in a low-power state).
Freescale Semiconductor
Core Interrupt Type
External interrupt
Critical interrupt
Machine check
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Programming model compliant with the OpenPIC architecture
Support for 12 external and 48 internal interrupt sources.
sources are implemented.) Serial interrupts are not supported.
Four interprocessor interrupt channels.
Four 32-bit messaging interrupt channels.
Eight shared message signaled interrupt sources and up to 32 sharers for shared interrupt register.
Four global high-resolution timers that can be clocked with the platform clock or the RTC input.
Fully-nested interrupt delivery
Processor initialization control
Programmable resetting of the PIC unit through the global configuration register
16 programmable interrupt priority levels
Support for connection of external interrupt controller device such as an 8259 programmable
interrupt controller
In 8259 mode, it generates a local (internal) interrupt output signal, IRQ_OUT.
Recovery from spurious interrupts
Table 10-1. Processor Interrupts Generated Outside the Core—Types and Sources
Features
Interrupts to the Processor Core
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
(Input to Core)
Signaled by
core_mcp
cint
int
Other Interrupts Generated Outside the Core
Generated by the PIC, as described in
Generated by the PIC, as described in
• MCP
• SRESET
• Assertion of core_mcp by global utilities block
PIC—Programmable Interrupts
(Table 10-5
Sources
Section 10.1.5, “Interrupt Sources.”
Section 10.1.5, “Interrupt Sources.”
Table
10-1) cause interrupts to the core
lists which of the 48 internal
Programmable Interrupt Controller
10-3