MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1171

MPU POWERQUICC III 783-PBGA

MPC8544VTALF

Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8544VTALF

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Table 19-4
Freescale Semiconductor
1
10–15
17–25
26–30
2:1 CCB to SYSCLK clock ratio may not be selected when PCI_clk_sel are configured to run off of SYSCLK.
Offset 0xE_0000
Bits
Reset 0 0 0 0 0 0 0
0–9
16
31
W
R
0
PCI_clk_sel Clock used for PCI. This bit corresponds to the values on cfg_pci_clk_sel at the negation of HRESET:
e500_Ratio
Plat_Ratio
describes the bit settings of PORPLLSR.
Name
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
Clock ratio between the e500 core and the CCB clock. The 3 lsbs of this field correspond to the values
on cfg_core_pll[0:2] at the negation of HRESET. Patterns not shown are reserved.
0000101:1
0000113:2
0001002:1
0001015:2
0 PCI runs off of PCI_CLK
1 PCI runs off of SYSCLK
Reserved
Clock ratio between the CCB (platform) clock and SYSCLK. The 4 lsbs correspond to the values on
cfg_sys_pll[0:3] at the negation of HRESET. Patterns not shown are reserved.
000102:1
000113:1
001004:1
001015:1
001106:1
Reserved
0
0
Figure 19-1. POR PLL Status Register (PORPLLSR)
0 n n n n n n
9 10
1
Table 19-4. PORPLLSR Field Descriptions
e500_Ratio
15
PCI_clk_sel
1
16
n
Description
17
n
0001103:1
0001117:2
0010004:1
0010019:2
010008:1
010019:1
0101010:1
0110012:1
1000016:1
1110120:1
0 0 0 0 0
0
0
25 26
0 n n n n n
Access: Read Only
Plat_Ratio
Global Utilities
30
31
0
n
19-5

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