MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 14

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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9.4.1
9.4.1.1
9.4.1.2
9.4.1.3
9.4.1.4
9.4.1.5
9.4.1.6
9.4.1.7
9.4.1.8
9.4.1.9
9.4.1.10
9.4.1.11
9.4.1.12
9.4.1.13
9.4.1.14
9.4.1.15
9.4.1.16
9.4.1.17
9.4.1.18
9.4.1.19
9.4.1.20
9.4.1.21
9.4.1.22
9.4.1.23
9.4.1.24
9.4.1.25
9.4.1.26
9.4.1.27
9.4.1.28
9.4.1.29
9.4.1.30
9.4.1.31
9.5
9.5.1
9.5.1.1
9.5.2
9.5.3
9.5.4
9.5.4.1
9.5.5
9.5.6
xiv
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Functional Description................................................................................................... 9-41
Register Descriptions................................................................................................. 9-11
DDR SDRAM Interface Operation............................................................................ 9-45
DDR SDRAM Address Multiplexing........................................................................ 9-47
JEDEC Standard DDR SDRAM Interface Commands ............................................. 9-52
DDR SDRAM Interface Timing................................................................................ 9-54
DDR SDRAM Mode-Set Command Timing............................................................. 9-58
DDR SDRAM Registered DIMM Mode ................................................................... 9-59
Chip Select Memory Bounds (CSn_BNDS).......................................................... 9-11
Chip Select Configuration (CSn_CONFIG).......................................................... 9-11
DDR SDRAM Timing Configuration 3 (TIMING_CFG_3)................................. 9-13
DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)................................. 9-14
DDR SDRAM Timing Configuration 1 (TIMING_CFG_1)................................. 9-16
DDR SDRAM Timing Configuration 2 (TIMING_CFG_2)................................. 9-18
DDR SDRAM Control Configuration (DDR_SDRAM_CFG)............................. 9-20
DDR SDRAM Control Configuration 2 (DDR_SDRAM_CFG_2)...................... 9-23
DDR SDRAM Mode Configuration (DDR_SDRAM_MODE)............................ 9-25
DDR SDRAM Mode 2 Configuration (DDR_SDRAM_MODE_2)..................... 9-26
DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL)................. 9-26
DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) ................. 9-29
DDR SDRAM Data Initialization (DDR_DATA_INIT) ....................................... 9-29
DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL) ............................. 9-30
DDR Initialization Address (DDR_INIT_ADDR)................................................ 9-30
DDR Initialization Enable Extended Address (DDR_INIT_EXT_ADDR) .......... 9-31
DDR IP Block Revision 1 (DDR_IP_REV1)........................................................ 9-32
DDR IP Block Revision 2 (DDR_IP_REV2)........................................................ 9-32
Memory Data Path Error Injection Mask High (DATA_ERR_INJECT_HI) ........ 9-33
Memory Data Path Error Injection Mask Low (DATA_ERR_INJECT_LO)........ 9-33
Memory Data Path Error Injection Mask ECC (ERR_INJECT)........................... 9-34
Memory Data Path Read Capture High (CAPTURE_DATA_HI)......................... 9-34
Memory Data Path Read Capture Low (CAPTURE_DATA_LO) ........................ 9-35
Memory Data Path Read Capture ECC (CAPTURE_ECC).................................. 9-35
Memory Error Detect (ERR_DETECT)................................................................ 9-35
Memory Error Disable (ERR_DISABLE)............................................................. 9-36
Memory Error Interrupt Enable (ERR_INT_EN).................................................. 9-37
Memory Error Attributes Capture (CAPTURE_ATTRIBUTES).......................... 9-38
Memory Error Address Capture (CAPTURE_ADDRESS) .................................. 9-39
Memory Error Extended Address Capture (CAPTURE_EXT_ADDRESS)......... 9-40
Single-Bit ECC Memory Error Management (ERR_SBE) ................................... 9-40
Supported DDR SDRAM Organizations............................................................... 9-45
Clock Distribution ................................................................................................. 9-57
Contents
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Freescale Semiconductor
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