MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 850
![MPU POWERQUICC III 783-PBGA](/photos/37/62/376266/mpc8544e_image_sml.jpg)
MPC8544VTALF
Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544VTALF
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Enhanced Three-Speed Ethernet Controllers
15.5.4.3.2
Figure 15-108
Table 15-112
15-118
10–15
Offset 0x01
Reset 0
Bits
Bits
0–6
6
7
8
9
7
8
9
W
R
0
Reset AN Reset auto-negotiation. This bit is cleared by default and is self-clearing.
Speed[1] Speed selection. This bit defaults to a set state and should always be set, which corresponds to 1000 Mbps
Duplex
Extend
Status
Name
Name
Full
0
Pre
No
—
—
—
—
0
describes the fields of the SR register.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
describes the definition for the SR register.
Status Register (SR)
—
0
Reserved, should be cleared.
This bit indicates that PHY status information is also contained in the Register 15, Extended Status Register.
Returns 1 on read. This bit is read-only.
Reserved, should be cleared.
MF preamble suppression enable. This bit indicates whether or not the PHY is capable of handling MII
management frames without the 32-bit preamble field. Returns 1, indicating support for suppressed
preamble MII management frames. This bit is read-only.
0 Normal operation.
1 The auto-negotiation process restarts. This action is only available if auto-negotiation is enabled.
Duplex mode. This bit is set by default.
0 Reserved.
1 Full-duplex operation.
Reserved, should be cleared.
speed.Setting this field controls the speed at which the TBI operates. The following table provides the
appropriate encoding. Its default is bit[2] = ‘0’; bit[9] = ’1’.
Reserved
0
0
0
6
Table 15-111. CR Field Descriptions (continued)
Extend
Status
1
Figure 15-108. Status Register Definition
7
Reserved
Reserved
1000 Mbps
Reserved
Maximum Operating Speed
Table 15-112. SR Descriptions
—
0
8
No Pre
1
9
AN Done
10
0
Description
Description
Remote
Bit 2
Fault
11
0
1
0
1
0
AN Ability
Bit 9
0
0
1
1
12
1
Status
Link
Freescale Semiconductor
13
0
Access: Read only
—
14
0
Extend
Ability
15
1
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