MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1283

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
0x2_41C0–
0x2_4240–
0x2_4308–
0x2_4318–
0x2_41BC
0x2_41FC
0x2_420C
0x2_421C
0x2_422C
0x2_423C
0x2_42FC
0x2_430C
0x2_432C
0x2_433C
0x2_41B8
0x2_4200
0x2_4204
0x2_4208
0x2_4210
0x2_4214
0x2_4218
0x2_4220
0x2_4224
0x2_4228
0x2_4230
0x2_4234
0x2_4238
0x2_4300
0x2_4304
0x2_4310
0x2_4314
0x2_4330
0x2_4334
0x2_4338
0x2_4340
Offset
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
TBPTR7*—TxBD pointer for ring 7
Reserved
TBASEH—TxBD base address high bits
TBASE0—TxBD base address of ring 0
Reserved
TBASE1*—TxBD base address of ring 1
Reserved
TBASE2*—TxBD base address of ring 2
Reserved
TBASE3*—TxBD base address of ring 3
Reserved
TBASE4*—TxBD base address of ring 4
Reserved
TBASE5*—TxBD base address of ring 5
Reserved
TBASE6*—TxBD base address of ring 6
Reserved
TBASE7*—TxBD base address of ring 7
Reserved
RCTRL—Receive control register
RSTAT—Receive status register
Reserved
RXIC—Receive interrupt coalescing register
RQUEUE*—Receive queue control register.
Reserved
RBIFX*—Receive bit field extract control register
RQFAR*—Receive queue filing table address register
RQFCR*—Receive queue filing table control register
RQFPR*—Receive queue filing table property register
MRBLR—Maximum receive buffer length register
eTSEC Receive Control and Status Registers
Table B-1. Memory Map (continued)
Register
Complete List of Configuration, Control, and Status Registers
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0080_0080
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
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B-17