MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1251

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 21-19
21.3.2.6
The trace buffer access control register (TBACR) enables software to read or write the trace buffer. Each
entry is 64 bits; therefore, it takes one write of TBACR and two reads of the access data register (TBADR
and TBADHR) to read one 256-entry array entry. Similarly, it takes one write of TBACR and two writes
of TBADR and TBADHR to write one array entry. Software can access any entry by writing the
appropriate index into TBACR[INDX]. To read or write the buffer sequentially, starting with entry 0, the
index must start with a value of 0 and increment every time a new entry is accessed.
TBACR is shown in
Freescale Semiconductor
24–31
4–23
Bits
Offset 0x060
Reset
0
1
2
3
W
R
RD
C_INDX Current index. Represents the current value of the write pointer at the time TBSR was read. This value
0
WRAP
Name
TRIG
ACT
STP
—
describes the TBSR fields.
Trace Buffer Access Control Register (TBACR)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
WR
1
Active. Indicates trace buffer activity.
0 The start triggering event has not yet occurred. Trace buffer is not armed.
1 The start triggering event has occurred. Trace buffer is armed.
Triggered. Indicates whether or not a programmed event has been triggered.
0 The programmed event in TBCR0 has not yet been triggered.
1 The programmed event in TBCR0 has been triggered at least once.
Stopped. Indicates whether or not a trace buffer stop condition has been detected.
0 No stop condition yet detected.
1 The trace buffer has detected a stop condition and is no longer capturing events.
Wrapped. Indicates that the trace buffer write pointer has wrapped to the beginning of the buffer at least
once. Set when the last entry of the trace buffer is written.
0 Pointer has not yet wrapped.
1 Pointer has wrapped to the beginning at least once.
Reserved
may be written by software to initialize the write pointer; however, software is not allowed to write the write
pointer while the trace buffer is active. Writes are ignored while the trace buffer is active. It is recommended
to write the status register before enabling the trace buffer in order to zero out any bits that might have
been set during a prior run and to initialize the write pointer to zero.
2
Figure
Figure 21-14. Trace Buffer Access Control Register (TBACR))
21-14.
Table 21-19. TBSR Field Descriptions
—
All zeros
Description
Debug Features and Watchpoint Facility
23 24
Access: Read/Write
INDX
31
21-21