MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1240

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Debug Features and Watchpoint Facility
21.3
Table 21-6
4-byte address spaces within offset 0x000–0xFFF are reserved.
In this table and in the register figures and field descriptions, the following access definitions apply:
21-10
0xE_200C WMAR—Watchpoint monitor address register
0xE_201C WMSR—Watchpoint monitor status register
0xE_204C TBAR—Trace buffer address register
0xE_205C TBSR—Trace buffer status register
0xE_20A0 PCIDR—Programmed context ID register
0xE_20A4 CCIDR—Current context ID register
0xE_2000
0xE_2004
0xE_2014
0xE_2018
0xE_2040
0xE_2044
0xE_2054
0xE_2058
0xE_2060
0xE_2064
0xE_2068
Memory
Offset
Local
•
•
•
•
•
Reserved fields are always ignored for the purposes of determining access type.
R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
Mixed indicates a combination of access types.
Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
Memory Map/Register Definition
shows the memory-mapped debug and watchpoint registers of the MPC8544E. Undefined
WMCR0—Watchpoint monitor control register 0
WMCR1—Watchpoint monitor control register 1
WMAMR—Watchpoint monitor address mask register
WMTMR—Watchpoint monitor transaction mask register
TBCR0—Trace buffer control register 0
TBCR1—Trace buffer control register 1
TBAMR—Trace buffer address mask register
TBTMR—Trace buffer transaction mask register
TBACR—Trace buffer access control register
TBADHR—Trace buffer access data high register
TBADR—Trace buffer access data register
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 21-6. Debug and Watchpoint Monitor Memory Map
Register
Watchpoint Monitor Registers
Trace Buffer Registers
Context ID Registers
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
Freescale Semiconductor
21.3.1.1/21-11
21.3.1.1/21-11
21.3.1.2/21-13
21.3.1.3/21-14
21.3.1.4/21-14
21.3.1.5/21-16
21.3.2.1/21-16
21.3.2.1/21-16
21.3.2.2/21-19
21.3.2.3/21-19
21.3.2.4/21-20
21.3.2.5/21-20
21.3.2.6/21-21
21.3.2.7/21-22
21.3.2.8/21-22
21.3.3.1/21-23
21.3.3.2/21-24
Section/Page