MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 979

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 16-26
Figure 16-27
16.4.5
This section addresses some of the limitations and restrictions of the DMA controller and is intended to
help software maximize the DMA performance and avoid DMA programming errors.
The limitations of the DMA controller are the following:
The DMA controller restrictions are as follows:
Freescale Semiconductor
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Due to the limited number of buffers that the DMA controller can use, stride sizes less than 64 bytes
should be avoided. Maximum utilization is obtained from strides greater than or equal to 256 bytes.
However, small stride sizes can be used for scatter-gather functions.
Coherent reads or writes are broken up into cache line accesses in the DMA.
All interface capabilities from where descriptors are being fetched must support read sizes of 32
bytes or greater.
If MRn[SAHE] is set, the source interface transfer size capability must be greater than or equal to
MRn[SAHTS]. The source address must be aligned to a size specified by SAHTS.
Limitations and Restrictions
describes the format of the list descriptors.
describes the format of the link descriptors.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Offset
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
Figure 16-27. Link Descriptor Format
Figure 16-26. List Descriptor Format
First Link Descriptor Extended Address
Next Link Descriptor Extended Address
Next List Descriptor Extended Address
Next Link Descriptor Address
First Link Descriptor Address
Next List Descriptor Address
Destination Attributes
Destination Address
Destination Stride
Source Attributes
Source Address
Source Stride
Reserved
Reserved
Byte Count
Reserved
DMA Controller
16-37