MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1180

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Global Utilities
Table 19-14
19.4.1.12 Device Disable Register (DEVDISR)
DEVDISR, shown in
1
All functional blocks are enabled after reset; unneeded blocks can be disabled to reduce power
consumption.
19-14
Offset
Reset
Reset
Bits
16–30
0–14
* n bits depend on the state of the corresponding POR configuration signals at reset.
Bits
0
1
15
31
W
W
R
R
E500
PCI
16
Name
0
PCI
—
Name
DMA2
DMA3
—
—
describes the bit settings of PMUXCR.
TB
17
0
1
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PCI controller disable
0 PCI controller enable
1 PCI controller disable
Reserved
PCIE1
Reserved
Enables DMA channel 2 signals.
0 DMA channel 2 is not exposed to pins; the pins retain their primary function as local bus chip selects
1 DMA channel 2 is exposed to pins as follows:
Reserved
Enables DMA channel 3 signals.
0 DMA channel 3 is not exposed to pins; the pins retain their primary function as interrupt requests.
1 DMA channel 3 is exposed to pins as follows:
18
0
2
Figure
LCS5 functions as DMA_DREQ2
LCS6 functions as DMA_DACK2
LCS7 functions as DMA_DDONE2
IRQ9 functions as DMA_DREQ3
IRQ10 functions as DMA_DACK3
IRQ11 functions as DMA_DDONE3
19
0
0
3
Figure 19-12. Device Disable Register (DEVDISR)
20-13, contains disable bits for various MPC8544E functional blocks.
LBC PCIE2 PCIE3 SEC
20
0
4
Table 19-15. DEVDISR Field Descriptions
Table 19-14. PMUXCR Field Descriptions
DMA
21
5
22
0
6
00 n 0_0 nn 0_0000_0000
0000_0000_0000_0000
23
0
7
0xE_0070
TSEC1
24
0
8
Description
Description
25
0
0
1
1
TSEC3
26
9
0
11
27
0
0
12
28
0
0
Freescale Semiconductor
I2C
13
29
0
DUART
14
30
0
DDR
15
31
0