MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 459

MPU POWERQUICC III 783-PBGA

MPC8544VTALF

Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8544VTALF

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
All I
1
11.3.1
This section describes the I
Freescale Semiconductor
0x100–
I
0x100 to 0x114.
Offset
0x00C
0x000
0x004
0x008
0x010
0x014
0x114
2
C2 has the same memory-mapped registers that are described for I
2
C registers are one byte wide. Reads and writes to these registers must be byte-wide operations.
I2CADR—I
I2CFDR—I
I2CCR—I
I2CSR—I
I2CDR—I
I2CDFSRR—I
I
2
C2 Registers
Register Descriptions
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved bits should always be written with the value they returned when
read. That is, the register should be programmed by reading the value,
modifying appropriate fields, and writing back the value. The return value
of the reserved fields should not be assumed, even though the reserved fields
return zero.
This note does not apply to the I
2
2
2
C status register
C control register
C data register
2
2
C frequency divider register
C address register
2
1
C digital filter sampling rate register
2
C registers in detail.
I
2
C Register
Table 11-3. I
Block Base Address: 0x0_3000
Block Base Address: 0x0_3000
I
I
2
2
2
C1 Registers
C2 Registers
C data register (I2CDR).
NOTE
2
C Memory Map
2
C1 from 0x000 to 0x014, except the offsets range from
Access
Mixed
Mixed
R/W
R/W
R/W
R/W
Reset
0x2C
0x00
0x00
0x81
0x00
0x10
11.3.1.5/11-10
11.3.1.6/11-11
Section/Page
11.3.1.1/11-6
11.3.1.2/11-6
11.3.1.3/11-7
11.3.1.4/11-9
I
2
C Interfaces
11-5

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