MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 796

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
15.5.3.3.12 Receive Descriptor Base Address High Register (RBASEH)
The RBASEH register is written by the user with the most significant address bits common to all RxBD
addresses, including RBASE0–RBASE7 and RBPTR0–RBPTR7. As a consequence, RxBD rings must be
placed in a 4 Gbyte segment of memory whose base address is prefixed by the bits in RBASEH. However,
Rx data buffers may potentially reside in a different memory region based at RBDBPH.
describes the definition for the RBASEH register.
Table 15-24
15.5.3.3.13 Receive Descriptor Base Address Registers (RBASE0–RBASE7)
The RBASEn registers are written by the user with the base address of each RxBD ring n. Each such value
must be divisible by eight, since the 3 least-significant bits always write as 000.
RBASEn registers.
Table 15-25
15-64
28–31
29–31
0–27
0–28
Bits
Bits
Offset eTSEC1:0x2_4400; eTSEC3:0x2_5400
Reset
Offset eTSEC1:0x2_4404+8× n ; eTSEC3:0x2_5404+8× n ××
Reset
W
W
R
R
RBASE n Receive base for ring n . RBASE defines the starting location in the memory map for the eTSEC RxBDs.
RBASEH Most significant bits common to all RxBD addresses—except data buffer pointers. The user must initialize
Name
0
0
Name
—
—
describes the fields of the RBASEH register.
describes the fields of the RBASEn registers.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
This field must be 8-byte aligned. Together with setting the W (wrap) bit in the last BD, the user can select
how many BDs to allocate for the receive packets. The user must initialize RBASE before enabling the
eTSEC receive function on the associated ring.
Reserved
Reserved
RBASEH before enabling the eTSEC receive function.
Table 15-38. RBASE0–RBASE7 Field Descriptions
Figure 15-34. RBASEH Register Definition
Table 15-37. RBASEH Field Descriptions
Figure 15-35. RBASE Register Definition
RBASE n
—
All zeros
All zeros
Description
Description
Figure 15-35
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
Figure 15-34
27 28
describes the
28 29
RBASEH
—
31
31