MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1078

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PCI Express Interface Controller
18.3.5.2
There are differences between RC and EP implementations of inbound ATMU registers as described in the
following sections.
18.3.5.2.1
All base address registers (BARs) reside in the PCI Express type 0 configuration header space which is
accessible via PEX_CONFIG_ADDR/PEX_CONFIG_DATA mechanism. Note that host software must
program these BAR using configuration type 0 cycles. There are 4 inbound BARs.
The PCI Express controller does not implement a shadow of the inbound BARs in the memory-mapped
register set. However, when there is a hit to the BAR(s), the PCI Express controller uses the corresponding
translation and attribute registers in the memory-mapped register set for the translation. If the transaction
hits multiple BARs, then the lowest-numbered BAR will be used.
18-24
20–25
26–31
Bits
•
•
•
•
Default inbound window BAR0 at configuration address 0x10 (32-bit). Also known as
PEXCSRBAR. This is a fixed 1-Mbyte window used for inbound memory transactions that access
memory-mapped registers.
Inbound window BAR1 at configuration address 0x14 (32-bit)
Inbound window BAR2 at configuration address 0x18-0x1c (64-bit)
Inbound window BAR3 at configuration address 0x20-0x24 (64-bit)
Name
OWS
—
PCI Express Inbound ATMU Registers
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
EP Inbound ATMU Implementation
Reserved
Outbound window size. Outbound translation window size N which is the encoded 2
The smallest window size is 4 Kbytes. Note that for the default window (window 0), the outbound window
size may be programmed less than the 64-Gbyte maximum. However, accesses that miss all other windows
and hit outside the default window will be aliased to the default window.
000000 Reserved
...
001011 4-Kbyte window size
001100 8-Kbyte window size
...
011111 4-Gbyte window size
100000 8-Gbyte window size
100001 16-Gbyte window size
100010 32-Gbyte window size
100011 64-Gbyte window size
100100 Reserved
...
111111 Reserved
Table 18-18. PEXOWAR n Field Descriptions (continued)
Description
Freescale Semiconductor
(N + 1)
-byte window size.