MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 385

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The auto-refresh commands are staggered across the four possible banks to reduce the system’s
instantaneous power requirements. Three sets of auto refresh commands will be issued on consecutive
cycles when the memory is fully populated with two DIMMs. The initial PRECHARGE-ALL commands
are also staggered in three groups for convenience. It is important to note that when entering self-refresh
mode, only one refresh command is issued simultaneously to all physical banks. For this entire refresh
sequence, no cycle optimization occurs for the usual case where fewer than four banks are installed. After
the refresh sequence completes, any pending memory request is initiated after an inactive period specified
by TIMING_CFG_1 [REFREC] and TIMING_CFG_3[EXT_REFREC]. In addition, posted refreshes are
supported to allow the refresh interval to be set to a larger value.
9.5.8.1
Refresh timing for the DDR SDRAM is controlled by the programmable timing parameter
TIMING_CFG_1 [REFREC], which specifies the number of memory bus clock cycles from the refresh
command until a logical bank activate command is allowed. The DDR memory controller implements
bank staggering for refreshes, as shown in
example).
System software is responsible for optimal configuration of TIMING_CFG_1 [REFREC] and
TIMING_CFG_3[EXT_REFREC] at reset. Configuration must be completed before DDR SDRAM
accesses are attempted.
9.5.8.2
In full-on mode, the DDR memory controller supplies the normal auto refresh to SDRAM. In sleep mode,
the DDR memory controller can be configured to take advantage of self-refreshing SDRAMs or to provide
no refresh support. Self-refresh support is enabled with the SREN memory control parameter.
Freescale Semiconductor
SDRAM Clock
MCS[0,3]
MRAS
MCAS
DDR SDRAM Refresh Timing
MCS1
MCS2
DDR SDRAM Refresh and Power-Saving Modes
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
CKE
MA n
Figure 9-45. DDR SDRAM Bank Staggered Auto Refresh Timing
0
1
2
3
Figure 9-45
4
5
6
(TIMING_CFG_1 [REFREC] = 10 in this
REFREC
7
8
9
10
11
0 or 3
ROW
12
DDR Memory Controller
13
14
9-61