MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 55

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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Freescale Semiconductor
UPM Read Access Data Sampling...................................................................................... 14-71
Burst Read Access to FPM DRAM Using LOOP (Two Beats Shown).............................. 14-76
SDRAM Read-After-Read Pipelined, Page Hit, CL = 3..................................................... 14-56
SDRAM Write-After-Write Pipelined, Page Hit................................................................. 14-56
SDRAM Read-After-Write Pipelined, Page Hit ................................................................. 14-57
SDRAM MODE-SET Command........................................................................................ 14-57
SDRAM Bank-Staggered Auto-Refresh Timing ................................................................ 14-58
User-Programmable Machine Functional Block Diagram.................................................. 14-59
RAM Array Indexing .......................................................................................................... 14-60
Memory Refresh Timer Request Block Diagram ............................................................... 14-61
UPM Clock Scheme............................................................................................................ 14-64
RAM Array and Signal Generation .................................................................................... 14-64
RAM Word Field Descriptions ........................................................................................... 14-65
LCSn Signal Selection ........................................................................................................ 14-68
LBS Signal Selection .......................................................................................................... 14-68
Effect of LUPWAIT Signal ................................................................................................. 14-72
Single-Beat Read Access to FPM DRAM .......................................................................... 14-74
Single-Beat Write Access to FPM DRAM ......................................................................... 14-75
Refresh Cycle (CBR) to FPM DRAM ................................................................................ 14-77
Exception Cycle .................................................................................................................. 14-78
Multiplexed Address/Data Bus ........................................................................................... 14-79
Local Bus Peripheral Hierarchy.......................................................................................... 14-80
Local Bus Peripheral Hierarchy for Very High Bus Speeds ............................................... 14-81
GPCM Address Timings ..................................................................................................... 14-81
GPCM Data Timings........................................................................................................... 14-82
Interface to Different Port-Size Devices ............................................................................. 14-84
128-Mbyte SDRAM Diagram............................................................................................. 14-88
SDRAM Power-Down Timing............................................................................................ 14-92
SDRAM Self-Refresh Mode Timing .................................................................................. 14-93
Local Bus PLL Operation ................................................................................................... 14-95
Parity Support for SDRAM................................................................................................. 14-96
Interface to ZBT SRAM ..................................................................................................... 14-97
MSC8101 HDI16 Peripheral Registers............................................................................... 14-99
Interface to MSC8101 HDI16........................................................................................... 14-100
Interface to MSC8102 DSI in Asynchronous Mode ......................................................... 14-103
Asynchronous Write to MSC8102 DSI............................................................................. 14-104
Asynchronous Read from MSC8102 DSI......................................................................... 14-105
Interface to MSC8102 DSI in Synchronous Mode ........................................................... 14-106
UPM Synchronization Cycle ............................................................................................ 14-107
Synchronous Single Write to MSC8102 DSI.................................................................... 14-108
Synchronous Single Read from MSC8102 DSI................................................................ 14-109
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
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