MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 988

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PCI Bus Interface
The master part of the interface can initiate master-abort cycles, recognizes target-abort, target-retry, and
target-disconnect cycles, and supports various device selection timings. The master interface does not run
fast back-to-back or exclusive accesses.
17.1.1.2
Upon detection of a PCI address phase, the integrated processor decodes the address and bus command to
determine if the transaction is within the local memory access boundaries. If the transaction is destined for
local memory, the target interface latches the address, decodes the PCI bus command, and forwards the
transaction to the OCeaN control unit. On writes to local memory, data is forwarded along with the byte
enables (if applicable) to the internal control unit. Note that for inbound writes less than 4-bytes, the PCI
controller splits the transaction into single byte writes to the target. Thus, the PCI interface cannot be used
to perform single beat writes to 16-bit devices on the local bus interface. On reads, the data is driven on
the bus and the byte enables (if applicable) determine which byte lanes contain meaningful data.
The target interface of the integrated processor can issue target-abort, target-retry, and target-disconnect
cycles. The target interface supports fast back-to-back transactions. The target interface uses the fastest
device selection timing.
The integrated processor supports data streaming to and from local memory. This means that data can flow
between the processor PCI interface and local memory as long as the internal buffers are not filled.
17.1.2
The following is a list of PCI features that is supported:
17.1.3
A number of parameters that affect the PCI controller modes of operation are determined at power-on reset
(POR) by reset configuration signals as described in
Table 17-1
17-4
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PCI interface 2.2 compatible
66- and 33-MHz support
32-bit PCI interface support on PCI port
Host and agent mode support
64-bit dual address cycle (DAC) support
On-chip arbitration with support for five high-priority request and grant signal pairs
Support for accesses to all PCI memory and I/O address spaces
Support for PCI-to-memory and memory-to-PCI streaming
Memory prefetching of PCI read accesses
Support posting of processor-to-PCI and PCI-to-memory writes
Support selectable snoop for inbound accesses
PCI configuration registers
PCI 3.3-V compatible
provides a summary of these modes.
Features
Modes of Operation
Inbound Transactions
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Chapter 4, “Reset, Clocking, and Initialization.”
Freescale Semiconductor