MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1066

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Offset 0x014
Reset
PCI Express Interface Controller
The fields of the PCI Express configuration retry timeout register are described in
18.3.2.5
The PCI Express configuration register, shown in
controller.
The fields of the PCI Express configuration register are described in
18-12
28–29
4–31
W
0–26
Bits
R
Bits
1–3
27
30
31
0
0
Name
Name
SAC
SCC
RD
TC
SP
—
—
—
PCI Express Configuration Register (PEX_CONFIG)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Retry disable. This bit disables the retry of a configuration transaction that receives a CRS status response
packet.
0 Enable retry of a configuration transaction in response to receiving a CRS status response until the timeout
1 Disable retry of a configuration transaction regardless of receiving a CRS status response.
Reserved
Timeout counter. This is the value that is used to load the CRS response counter.
One TC unit is 24 ns at 333 MHz and 30 ns at 260 MHz.
Timeout period based on different TC settings:
0x000_0000
0x400_FFFF
0xFFF_FFFF 7.12 seconds at 333.33 MHz platform clock
Reserved
Sense ASPM Control. This bit controls the default value of ASPM of PEX Link Control Register’s bit 0. See
Section 18.3.9.11, “PCI Express Link Control Register—0x5C,”
Reserved
Slot Present. This bit controls the default value of the PCI Express capabilities register [slot] bit. See
Section 18.3.9.6, “PCI Express Capabilities Register—0x4E,”
Slot Clock Configuration. This bit controls the default value of the PCI Express link status register [SCC] bit.
See
counter (defined by the PEX_CONF_RTY_TOR[TC] field) has expired.
Section 18.3.9.12, “PCI Express Link Status Register—0x5E,”
Figure 18-6. PCI Express Configuration Register (PEX_CONFIG)
Table 18-7. PEX_CONF_RTY_TOR Field Descriptions
Reserved
1.612 seconds at 333.33 MHz platform clock
Table 18-8. PEX_CONFIG Field Descriptions
—
Figure
all zeros
Description
Description
18-6, contains various control switches for the
for more information.
for more information.
Table
for more information.
18-8.
Table
26
Freescale Semiconductor
SAC
27
18-7.
Access: Read/Write
28 29
—
SP
30
SCC
31