MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 762

MPU POWERQUICC III 783-PBGA

MPC8544VTALF

Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8544VTALF

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Enhanced Three-Speed Ethernet Controllers
15.5.3.1.5
Figure 15-6
disable an error interruption, possibly to avoid spurious error indications external to the eTSECs.
15-30
Offset eTSEC1:0x2_4018; eTSEC3:0x2_5018
Reset
Reset
17–19
25–27
Bits
14
15
16
20
21
22
23
24
28
29
30
31
W
W
R
R
16
0
MMWREN
MMRDEN
GRSCEN
PERREN
XFUNEN
MAGEN
CRLEN
RXBEN
DPEEN
RXFEN
FIREN
FIQEN
Name
describes the definition for the EDIS register. The error disabled register allows the user to
1
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Error Disabled Register (EDIS)
BSYDIS EBERRDIS
2
Collision retry limit enable
Transmit FIFO underrun enable
Receive buffer interrupt enable
Reserved
Magic Packet received interrupt enable
MII management read completion interrupt enable
MII management write completion interrupt enable
Graceful receive stop complete interrupt enable
Receive frame interrupt enable
Reserved
Filer invalid result interrupt enable
Filed frame to invalid queue interrupt enable
Data parity error interrupt enable
Receive frame parse error enable
3
Table 15-8. IMASK Field Descriptions (continued)
Figure 15-6. EDIS Register Definition
4
6
BABTDIS — TXEDIS
7
All zeros
All zeros
8
Description
9
10
27
FIRDIS FIQDIS DPEDIS PERRDIS
12
28
LCDIS CRLDIS XFUNDIS
13
29
Freescale Semiconductor
Access: Read/Write
14
30
15
31

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