MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 972

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DMA Controller
16.4.1.3
An external control can be used to control all DMA channels by setting MRn[EMS_EN]. The external
control can control the DMA channel in the following transfer modes:
Note that when operating the DMA in chaining mode the register byte count field, BCR[BC], must be
initialized to zero before enabling the pause feature. In chaining modes, the channel does not pause for
descriptor fetch transfer.
The external control and the DMA controller use a well defined protocol to communicate. The external
control can start or restart a paused DMA transfer. The DMA controller acknowledges a DMA transfer in
progress and also indicates a transfer completion.
The pause feature can be enabled by setting MRn[EMP_EN]. MRn[BWC] specifies how much data to
allow a specific channel to transfer before entering a paused state by clearing MRn[CS]. Note, however,
that write data for a paused transfer may not have reached the target interface when so indicated. The
channel can be restarted from a paused state by the asserted edge of DREQ as driven by an external master.
In chaining modes, the channel does not pause for descriptor fetch transfer. It only pauses during the actual
data transfer.
The following signals are defined for the external control interface:
Detailed descriptions of the external control interface are in
control interface is shown in
16-30
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Basic direct
Basic chaining
Extended direct
Extended chaining
DMA_DREQ - Asserting edge triggers a DMA transfer start or restart from a pause request. Sets
MRn[CS].
DMA_DACK - Indicates a DMA transfer currently in progress. SRn[CB] is set.
DMA_DDONE - Indicates the completion of the DMA controller’s involvement in the transfer and
the readiness to accept a new DMA command. SRn[CB] is clear. Note, however, that write data
may still be queued at the target interface or in the process of transfer on an external interface.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
External Control Mode Transfer
Figure
16-23.
Table
16-3. The timing diagram of the external
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