MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 616

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DUART
composite serial data stream on the channel transmitter serial data output (SOUT). The transmitter status
may be polled or interrupt-driven.
The receiver accepts serial data on the channel receiver serial data input (SIN), converts the data into
parallel format, and checks for START, STOP, and parity bits. In FIFO mode, the receiver removes the
START, STOP, and parity bits and then transfers the assembled character from the receiver buffer, or
receiver FIFO. This transfer occurs in response to a read of the UART receiver buffer register (URBR).
The receiver status may be polled or interrupt driven.
13.4.1
The UART bus is a serial, full-duplex, point-to-point bus as shown in
devices are attached to the same signals and there is no need for address or arbitration bus cycles.
A standard UART bus transfer is composed of either three or four parts:
An internal logic sample signal, rxcnt, uses the frequency of the baud-rate generator to drive the bits on
SOUT.
The following sections describe the four components of the serial interface, the baud-rate generator, local
loopback mode, different errors, and FIFO mode.
13.4.1.1
A write to the transmitter holding register (UTHR) generates a START bit on the SOUT signal.
Figure 13-16
new data transfer which is limited to the bit length programmed in the UART line control register
(ULCR).When the bus is idle, SOUT is high.
13-20
•
•
•
•
SOUT1
rxcnt
START
START bit
Data transfer bits (least-significant bit is first data bit on the bus)
Parity bit (optional)
STOP bits
Serial Interface
shows that the START bit is defined as a logic 0. The START bit denotes the beginning of a
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
D6 D5 D4 D3 D2 D1 D0 PTY
START Bit
1
2
Figure 13-16. UART Bus Interface Transaction Protocol Example
3
Data Bits
Two 7-bit data transmissions with parity and 2-bit STOP transactions
4
5
6
Even/Odd Parity
7
Optional
8
STOP Bits
9
10
START
D6 D5 D4 D3 D2 D1 D0 PTY
1
2
3
Figure
Data Bits
4
5
13-16. Therefore, only two
6
7
Freescale Semiconductor
Optional
Even/Odd Parity
8
STOP Bits
9
10