MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 765

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
20–24
Bits
18
19
25
26
27
28
29
30
31
SGMIIM
AUTOZ
R100M
GMIIM
Name
STEN
TBIM
RMM
RPM
—
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Automatically zero MIB counter values.
0 The user must write the addressed counter zero after a host read.
1 The addressed counter value is automatically cleared to zero after a host read.
This is a steady state signal and must be set prior to enabling the Ethernet controller and must not be
changed without proper care.
MIB counter statistics enabled.
0 Statistics not enabled
1 Enables internal counters to update
This is a steady state signal and must be set prior to enabling the Ethernet controller and must not be
changed without proper care.
Reserved
GMII interface mode. If this bit is set, a PHY with a GMII or RGMII interface is expected to be connected.
If cleared, a PHY with an MII or RMII interface is expected. The user should then set
MACCFG2[I/F Mode] accordingly. The state of this status bit is defined during power-on reset. See
Section 4.4.3, “Power-On Reset Configuration.”
0 MII or RMII mode interface expected
1 GMII or RGMII mode interface expected
Ten-bit interface mode. If this bit is set, ten-bit interface mode is enabled. This bit can be pin-configured
at reset to set or clear. See
0 GMII or MII or RMII mode interface
1 TBI mode interface
Ethernet and FIFO interfaces. RPM and RMM are never set together. This register can be
pin-configured at reset to 0 or 1. See
0 GMII or MII or TBI in non-reduced-pin mode configuration
1 RGMII or RTBI reduced-pin mode
RGMII/RMII 100 mode. This bit is ignored unless SGMIIM, RPM or RMM are set and MACCFG2[I/F
Mode] is assigned to 10/100 (01). If this bit is set, the eTSEC interface is in 100 Mbps speed.
0 RGMII is in 10 Mbps mode;
1 RGMII is in 100 Mbps mode;
Reduced-pin mode for 10/100 interfaces. If this bit is set, a RMII pin interface is expected. Valid only if
FIFM = 0 and TBIM = 0. RPM and RMM are never set together. This register can be pin-configured at
reset to 0 or 1. See
0 MII, RGMII, GMII, TBI, or RTBI mode configuration
1 RMII mode
Serial GMII mode. If this bit is set, a SGMII pin interface is expected to be connected via an on chip
SERDES.
This register can be pin-configured at reset to 0 or 1. See
Section 4.4.3.14, “eTSEC3 Protocol.”
0 SGMII mode disabled. eTSEC connected via a parallel interface.
1 SGMII mode enabled.
Reserved
Reduced-pin mode for Gigabit interfaces. If this bit is set, a reduced-pin interface is expected on either
SGMII is in 10 Mbps mode, and every 100th SGMII Reference clock is used to transfer data
SGMII is in 100 Mbps mode, and every 10th SGMII Reference clock is used to transfer data
FIFO configured for 8-bit operation
RMII is in 10 Mbps mode, and every 10th RMII Reference clock is used to transfer data
RMII is in 100 Mbps mode, and data is transferred on every Reference clock
Table 15-10. ECNTRL Field Descriptions (continued)
Section 4.4.3, “Power-On Reset Configuration.”
Section 4.4.3, “Power-On Reset Configuration.”
Section 4.4.3, “Power-On Reset
Description
Section 4.4.3.13, “eTSEC1 Protocol”
Enhanced Three-Speed Ethernet Controllers
Configuration.”
and
15-33