MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 960

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DMA Controller
Table 16-11
16.3.1.7
The destination address registers, shown in
controller writes data.
In direct mode, if MRn[SRW] is set and MRn[CDSM/SWSM] is cleared, a write to this register
simultaneously sets MRn[CS], starting a DMA transfer. Software must ensure that this is a valid address.
16-18
12–15
16–27
28–31
8–11
Bits
0–1
4–5
2
3
6
7
DWRITETTYPE DMA destination transaction type. Reserved values will result in a programming error being detected
DPCI_ORDER PCI ordering rules enable. Applicable only while DATR n [DBPATMU] is set.
DTFLOWLVL
DBPATMU
DSME
Name
EDAD
describes the fields of the DATRn.
—
—
—
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Destination Address Registers (DAR n )
Reserved
Bypass ATMU for this DMA operation
0 Route the operation through the ATMU outbound windows. DATR n [DWRITETTYPE] should
1 Bypass ATMU. Never generate an address match. Always use the attributes in the destination
Applicable only to RapidIO interface.
Reserved
RapidIO transaction flow level
00 Lowest priority transaction flow
01 Next highest priority transaction flow
10 Highest priority transaction flow
11 Reserved
Applicable only to RapidIO interface, while DATR n [DBPATMU] is set.
0 Retain original transaction ordering
1 Follow PCI transaction ordering rules on RapidIO (elevate write priority one level over reads).
Destination stride mode enable
0 Stride mode disabled
1 Stride mode enabled
Ignored in basic mode (MR n [XFE] is cleared). Striding on the destination address can be
accomplished by setting DSME and setting the desired stride size and distance in DSR n .
Reserved
and logged in SR[PE].Transaction type to run on local address space
0000–0011 Reserved
0100 Write, don’t snoop local processor
0101 Write, snoop local processor
0110 Write, allocate L2 cache line
0111 Write, allocate and lock L2 cache line
1000–1111 Reserved
Reserved
Extended destination address. EDAD represents the four high-order bits of the 36-bit destination
address.
specify a local address space transaction type.
attribute registers. Route the transaction to the interface specified in the DATR n [DTRANSINT]
field.
Table 16-11. DATR n Field Descriptions
Figure
16-12, contain the addresses to which the DMA
Description
Freescale Semiconductor