MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 647

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 14-18
14.3.1.13
Figure 14-16
LBC error registers to update following any subsequent errors.
Freescale Semiconductor
10–11
13–31
Bits
3–4
6–7
12
0
1
2
5
8
9
Offset 0x0BC
Reset
WARA Write-after-read atomic (WARA) error interrupt enable
RAWA Read-after-write atomic (RAWA) error interrupt enable
Name
PARI
BMI
WPI
CSI
W
—
—
—
—
—
R
describes LTEIR fields.
0
shows the LTEATR. After LTEATR[V] has been set, software must clear this bit to allow
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Bus monitor error interrupt enable
0 Bus monitor error reporting is disabled.
1 Bus monitor error reporting is enabled.
Reserved
Parity error interrupt enable. Note that uncorrectable read errors may cause the assertion of core_fault_in ,
which causes the core to generate a machine check interrupt, unless it is disabled (by clearing HID1[RFXE]).
If RFXE is zero and this error occurs, LTEDR[PARD] must be cleared and PARI must be set to ensure that an
interrupt is generated. For more information, see
Register 1 (HID1).”
0 Parity error reporting is disabled.
1 Parity error reporting is enabled.
Reserved
Write protect error interrupt enable
0 Write protect error reporting is disabled.
1 Write protect error reporting is enabled.
Reserved
0 WARA error reporting is disabled.
1 WARA error reporting is enabled.
0 RAWA error reporting is disabled.
1 RAWA error reporting is enabled.
Reserved
Chip select error interrupt enable
0 Chip select error reporting is disabled.
1 Chip select error reporting is enabled.
Reserved
—
Transfer Error Attributes Register (LTEATR)
2
RWB
3
Figure 14-16. Transfer Error Attributes Register (LTEATR)
4
Table 14-18. LTEIR Field Descriptions
—
10 11
SRCID
All zeros
Description
15 16
Section 6.10.2, “Hardware Implementation-Dependent
PB
19 20
BNK
Access: Read/Write
27 28 29 30 31
Local Bus Controller
XA — V
14-27