MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 109

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
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— 4-cycle integer pipelined multiplies
— 4-, 11-, 19-, and 35-cycle integer divides
— 4-cycle SIMD pipelined multiply-accumulate (MAC)
— 64-bit accumulator for MAC operations
Single-precision vector and scalar floating-point APUs
Load/store unit (LSU)
— 3-cycle load latency
— Fully pipelined
— Nine-entry load queue allows up to nine load misses before stalling
— Can continue servicing load hits when load queue is full
— Six-entry store queue allows full pipelining of stores
Cache coherency
— Bus support for hardware-enforced coherency (bus snooping)
Core complex bus (CCB)
— High-speed, on-chip local bus with data tagging
— 36-bit address bus
— 60x-like address protocol with address pipelining and retry/copyback
— Two general-purpose read data, one write data bus
— 128-bit data plus parity/tags (each data bus)
— Supports out-of-order reads, in-order writes
— Little to no data bus arbitration logic required for native systems
— Supports one-level pipelining of addresses with address-retry responses
Extended exception handling
— Supports Book E interrupt model
— e500-specific interrupts not defined in Book E architecture
Memory management unit (MMU)
— Data L1 MMU
– Interrupt vector prefix register (IVPR)
– Interrupt vector offset registers (IVORs) 0–15 as defined in Book E plus e500-defined
– Exception syndrome register (ESR)
– Book E–defined preempting critical interrupt, including critical interrupt status registers
– SPE APU unavailable exception
– Floating-point data exception
– Floating-point round exception
– Performance monitor
– Four-entry, fully-associative TLB array for variable-sized pages
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
IVORs 32–35
(CSRR0 and CSRR1) and an rfci instruction
Overview
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