MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 342

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DDR Memory Controller
9.4.1.6
DDR SDRAM timing configuration 2, shown in
9-18
16–19
21–23
25–27 ACTTOACT Activate-to-activate interval (t
29–31 WRTORD Last write data pair to read command issue interval (t
Offset 0x10C
Reset
Bits
20
24
28
W
R
— ADD_LAT
0
REFREC
WRREC
Name
1
—
—
—
DDR SDRAM Timing Configuration 2 (TIMING_CFG_2)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure 9-7. DDR SDRAM Timing Configuration 2 Register (TIMING_CFG_2)
Refresh recovery time (t
command is allowed. This field is concatenated with TIMING_CFG_3[EXTREFREC] to obtain a 7-bit value
for the total refresh recovery. Note that hardware adds an additional 8 clock cycles to the final, 7-bit value
of the refresh recovery, such that t
0000 8 clocks
0001 9 clocks
0010 10 clocks
Reserved, should be cleared.
Last data to precharge minimum interval (t
associated with a write command until a precharge command is allowed.
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
Reserved, should be cleared.
activate command is allowed for a different logical bank in the same physical bank (chip select).
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
Reserved, should be cleared.
data pair and the subsequent read command to the same physical bank.
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
3 4
CPO
Table 9-10. TIMING_CFG_1 Field Descriptions (continued)
8 9 10
— WR_LAT
RFC
12 13
). Controls the number of clock cycles from a refresh command until an activate
RRD
0011 11 clocks
…
1111 23 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
—
). Number of clock cycles from an activate command until another
RFC
15 16
Figure
is calculated as follows: t
RD_TO_PRE WR_DATA_DELAY — CKE_PLS
All zeros
WR
). Determines the number of clock cycles from the last data
Description
9-7, sets the clock delay to data for writes.
18
WTR
19
). Number of clock cycles between the last write
RFC
= {EXT_REFREC || REFREC} + 8.
21 22 23
Freescale Semiconductor
Access: Read/Write
25 26
FOUR_ACT
31