MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 963

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.3.1.10
The current list descriptor address registers, shown in
address of the list descriptor in memory in extended chaining mode.
In extended chaining mode, software must initialize CLSDARn and ECLSDARn to point to the first list
descriptor in memory. After finishing the last link descriptor in the current list, the DMA controller loads
the contents of the next list descriptor address register into the current list descriptor address register. If
NLSDARn[EOLSD] in the next list descriptor address register is clear, the DMA controller reads the new
current list descriptor from memory to process that list. If EOLSD in the next list descriptor address
register is set and the last link in the current list is finished all DMA transfers are complete.
Table 16-16
Freescale Semiconductor
Offset 0x134
Reset
Offset 0x130
Reset
W
27–31
R
0–26
W
Bits
R
0x1B4
0x234
0x2B4
0
0x1B0
0x230
0x2B0
0
describes the fields of the CLSDARn.
CLSDA
Name
Figure 16-16. Extended Current List Descriptor Address Registers (ECLSDAR n )
(CLSDAR n and ECLSDAR n )
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Current List Descriptor Address Registers
—
Figure 16-17. Current List Descriptor Address Registers (CLSDAR n )
Current list descriptor address. Contains the low-order bits of the 36-bit current list descriptor
address of the buffer descriptor in memory in extended chaining mode. The descriptor must be
aligned to a 32-byte boundary.
Reserved
Table 16-16. CLSDAR n Field Descriptions
CLSDA
—
All zeros
All zeros
Figure 16-17
Description
and
Table
16-16, contain the current
26
Access: Read/Write
Access: Read/Write
27
27 28
DMA Controller
—
ECLSDA
16-21
31
31