MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 792

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Table 15-33
15-60
0000 0–31
0001 0–15
0010
0011
0100
0101
PID
\
1
16–23
24–31
28-29
8–15
8–31
8–31
8–31
0–7
0–7
0–7
0–7
Bit
16
17
18
19
20
21
22
23
24
25
26
27
30
31
describes the fields of the RQFPR register.
MASK Mask bits to be written to Filer mask_register for masking of property values. The rule match/fail status
Name
UDP Set if a UDP header was parsed.
EBC Set if the destination Ethernet address is to the broadcast address.
JUM Set if a jumbo Ethernet frame was parsed.
TCP
PER Set on a parse error, such as header inconsistency.
EER Set on an Ethernet framing error that prevents parsing.
ARB User-defined arbitrary bit field property: byte 0 extracted. Defaults to 0x00.
DAH Destination MAC address, most significant 24 bits. Defaults to 0x000000.
SAH Source MAC address, most significant 24 bits. Defaults to 0x000000.
VLN
DAL
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
ICC
CFI
IPF
ICV
FIF
IP4
IP6
—
—
—
—
—
for this PID is determined by RQCTRL[CMP]. Since mask_register is bit-wise ANDed with properties,
every bit of MASK that is cleared also results in the corresponding property bit being cleared in
comparisons. Therefore setting MASK to 0xFFFF_FFFF ensures that all property bits participate in rule
matches.
Reserved
Set if a VLAN tag (Ethertype DFVLAN[TAG] or 0x8100) was seen in the frame.
Set to the value of the Canonical Format Indicator in the VLAN control tag if VLAN is set, zero otherwise.
Set if a fragmented IPv4 or IPv6 header was encountered.
See the descriptions of receive FCB fields IP and PRO in
more information on determining the status of received packets for which IPF is set.
Set if the packet entered on eTSEC’s FIFO interface.
Set if an IPv4 header was parsed.
Set if an IPv6 header was parsed.
Set if the IPv4 header checksum was checked.
Set if the IPv4 header checksum was verified correct.
Set if a TCP header was parsed.
Reserved.
User-defined arbitrary bit field property: byte 1 extracted. Defaults to 0x00.
User-defined arbitrary bit field property: byte 2 extracted. Defaults to 0x00.
User-defined arbitrary bit field property: byte 3 extracted. Defaults to 0x00.
Reserved, should be written with zero.
Reserved, should be written with zero.
Destination MAC address, least significant 24 bits. Defaults to 0x000000.
Reserved, should be written with zero.
Table 15-33. RQFPR Field Descriptions
Description
Section 15.6.4.3, “Receive Path
Freescale Semiconductor
Off-Load,” for