MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 45

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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1-3
1-4
1-5
1-6
1-7
1-8
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
3-1
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4-1
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4-6
4-7
5-1
5-2
5-3
5-4
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5-7
5-8
Freescale Semiconductor
MPC8544E Block Diagram .................................................................................................... 1-2
Integrated Security Engine Functional Blocks...................................................................... 1-16
Processing Transactions Across the On-Chip Fabric............................................................ 1-21
Multifunction Router Application Enabled by Local Bus, PCI Express,
Multifunction Printer Application Enabled by Local Bus, PCI Express,
Security Appliance Enabled by SEC, Local Bus, PCI, and Ethernet.................................... 1-24
IP SAN Host Adapter Enabled by Local Bus, PCI Express, and Ethernet ........................... 1-25
VoIP Aggregation Application Enabled by Local Bus and Ethernet .................................... 1-26
Local Memory Map Example ................................................................................................. 2-2
Local Access IP Block Revision Register 1 (LAIPBRR1) ..................................................... 2-6
Local Access IP Block Revision Register 2 (LAIPBRR2) ..................................................... 2-6
Local Access Window n Base Address Registers (LAWBAR0–LAWBAR7) ....................... 2-7
Local Access Window n Attributes Registers (LAWAR0–LAWAR7) ................................... 2-7
General Utilities Registers Mapping to Configuration, Control,
PIC Mapping to Configuration, Control, and Status Memory Block ................................... 2-13
Device-Specific Register Mapping to Configuration, Control,
MPC8544E Signal Groupings (1/3)........................................................................................ 3-2
MPC8544E Signal Groupings (2/3) (Continued).................................................................... 3-3
MPC8544E Signal Groupings (3/3) (Continued).................................................................... 3-4
Configuration, Control, and Status Register Base Address Register (CCSRBAR)................ 4-5
Alternate Configuration Base Address Register (ALTCBAR) ............................................... 4-6
Alternate Configuration Attribute Register (ALTCAR) ......................................................... 4-6
Boot Page Translation Register (BPTR) ................................................................................. 4-7
Power-On Reset Sequence .................................................................................................... 4-10
Clock Subsystem Block Diagram ......................................................................................... 4-24
RTC and Core Timer Facilities Clocking Options ................................................................ 4-26
e500 Core Complex Block Diagram ....................................................................................... 5-2
Vector and Floating-Point APUs............................................................................................. 5-5
Four-Stage MU Pipeline, Showing Divide Bypass................................................................. 5-7
Three-Stage Load/Store Unit .................................................................................................. 5-8
Instruction Pipeline Flow ...................................................................................................... 5-14
GPR Issue Queue (GIQ) ....................................................................................................... 5-15
e500 Core Programming Model............................................................................................ 5-17
MMU Structure ..................................................................................................................... 5-23
PCI, and Ethernet ............................................................................................................. 1-22
PCI, and Ethernet ............................................................................................................. 1-23
and Status Memory Block ................................................................................................ 2-12
and Status Memory Block ................................................................................................ 2-14
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
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