MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1233

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.1.2
The principal features of the debug modes and the watchpoint monitor are as follows:
21.1.3
The LBC, and DDR SDRAM interfaces all have debug modes, which are controlled by values on
configuration inputs during the power-on reset (POR) sequence, as shown in
controller can also drive debug information on either MSRCID[0:4] or MECC[0:5]. See
“Source and Target ID,”
signals in these modes.
Note that both the watchpoint monitor and trace buffer also operate in a variety of modes.
Freescale Semiconductor
Configuration
MSRCID0
MSRCID1
•
•
•
•
Signal
LBC and DDR interface source ID and data-valid indicators
— LBC or DDR SDRAM source ID can be selected to be driven onto MSRCID[0:4]
— Source ID and data-valid indicators can be selected to be driven onto the error correcting code
Watchpoint monitor that supports
— Two-level triggering
— Programmable external trigger (TRIG_OUT)
— Interlocked with performance monitor to use its large number of counters
Trace buffer features that support
— Two-level triggering
— Programmable external trigger (TRIG_OUT)
— Interlocked with performance monitor to use its large number of counters
— 256-entry trace buffer, 64 bits each
— Programmable trace start and stop
— Can function as a second watchpoint monitor
Context ID registers that can be programmed to trigger events
(ECC) pins of the DDR interface
Features
Modes of Operation
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Value
POR
0
1
0
1
Local bus SDRAM information appears on MSRCID[0:4] and MDVAL.
Default value (internal pull-up resistor). DDR SDRAM information appears on
MSRCID[0:4] and MDVAL.
MECC[0:4] operate in debug mode and provide memory debug source ID and
MECC5 provides data-valid information.
Default value (internal pull-up resistor). MECC[0:4] operate in normal mode and
provide DDR SDRAM error correcting code information.
Table 21-1. POR Configuration Settings and Debug Modes
for additional information about the source ID information driven on the debug
Effect
Debug Features and Watchpoint Facility
Table
21-1.The DDR
Section 21.4.1,
21.1.3.1/21-4
21.1.3.2/21-4
Reference
21-3