MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1263

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Appendix A
Revision History
This appendix provides a list of major differences between revisions of the MPC8544E
PowerQUICC™ III Integrated Host Processor Family Reference Manual.
A.1
Major changes to the MPC8544E PowerQUICC™ III Integrated Host Processor Family Reference
Manual, from Revision 0 to Revision 1, are as follows:
Section/Page
3.1/3-1
5.2/5-4
9.4.1.28/9-38
11.3.1.2/11-6
11.3.1.4/11-9
11.3.1.6/11-11
Chapter 15/15-1
15.4/15-6
Freescale Semiconductor
Changes From Revision 0 to Revision 1
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Added
In
In
000
001
010
011
Others Reserved
In
“serial bit clock frequency of SCL is equal to one half the platform (CCB) clock”
to
“serial bit clock frequency of SCL is equal to one third the platform (CCB) clock”
In
“I2CSR” to “I2CDR” for the received case conditions.
In
“sampling rate is calculated by dividing one half the platform (CCB clock)
frequency”
to
“sampling rate is calculated by dividing one third the platform (CCB clock)
frequency”
“eTSEC3” was sometimes referenced as “eTSEC2”; all references in the chapter
to “eTSEC2” should be changed to “eTSEC3”.
In
in the function description.
Table 15-1,
Table
Table
Table
Table
Table
Table
4 double words
1 double word
2 double words
3 double words
5-1, changed PVR/SVR values.
9-34, added to the bit field description of TSIZ:
11-5, corrected the bit field description of FDR from:
11-7, corrected the bit field description of MCF. Specifically, changed
11-9, corrected the bit field description of DFSR from:
3-2.
updated the descriptions of TXD[7:4] and RXD[7:4] to include MII
Changes
A-1